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PDF ispLSI1024EA-125LT100 Data sheet ( Hoja de datos )
| Número de pieza | ispLSI1024EA-125LT100 | |
| Descripción | In-System Programmable High Density PLD | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispLSI ® 1024EA
In-System Programmable High Density PLD
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 48 I/O Pins, Two Dedicated Inputs
— 144 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems (VCCIO Pin)
— Open-Drain Output Option
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 200 MHz Maximum Operating Frequency
— tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
A0 C7
DQ
A1 C6
A2 D Q
Logic
C5
A3 Array D Q GLB C4
A4 C3
A5 D Q C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
0139/1024EA
Description
The ispLSI 1024EA is a High Density Programmable
Logic Device containing 144 Registers, 48 Universal I/O
pins, two Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1024EA features 5V in-system
diagnostic capabilities via IEEE 1149.1 Test Access Port.
The ispLSI 1024EA device offers non-volatile
reprogrammability of the logic, as well as the intercon-
nects to provide truly reconfigurable systems. A functional
superset of the ispLSI 1024 architecture, the ispLSI
1024EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.
The basic unit of logic on the ispLSI 1024EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (Figure 1). There are a total of 24 GLBs in the
ispLSI 1024EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1024ea_01
1
1 page  
Specifications ispLSI 1024EA
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 3
Table 2-0003/1024EA
Figure 3. Test Load
Device
Output
Output Load Conditions (see Figure 3)
+ 5V
R1
R2
Test
Point
CL*
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.5V
Active Low to Z
at VOL+0.5V
R1
470Ω
∞
470Ω
∞
R2
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
470Ω
390Ω 5pF
Table 2-0004/1024EA
*CL includes Test Fixture and Probe Capacitance.
0213a
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL Output Low Voltage
IOL = 8 mA
—
— 0.4
V
VOH Output High Voltage
IOH = -2 mA, VCCIO = 3.0V
IOH = -4 mA, VCCIO = 4.75V
2.4 — — V
2.4 — — V
IIL
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
— — -10 µA
IIH
IIL-PU
IOS1
Input or I/O High Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
VCCIO ≤ VIN ≤ 5.25V
0V ≤ VIN ≤ VIL
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
— — 10 µA
— — 10 µA
— — -200 µA
— — -240 mA
ICC2, 4, 5 Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
— 152
— mA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
Table 2-0007/1024EA
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum ICC.
5
5 Page 
Specifications ispLSI 1024EA
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
GOE 0/IN 41
GOE 1/IN 51
TQFP PIN
NUMBERS
19, 20, 21, 22,
23, 28, 29, 30,
31, 32, 33, 34,
42, 43, 44, 45,
46, 47, 48, 53,
54, 55, 56, 57,
69, 70, 71, 72,
73, 78, 79, 80,
81, 82, 83, 84,
92, 93, 94, 95,
96, 97, 98, 3,
4, 5, 6, 7
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
91 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
8 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
TDI
TMS
TDO
TCK
18
68
35
58
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
Input - Controls the operation of the ISP state machine.
Output - Functions as an output pin to read serial shift register data.
Input - Functions as a clock pin for the Serial Shift Register.
RESET
Y0
Y1
17
9
67
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Y2 60
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Y3 59
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
GND
VCC
14, 15, 36, 37, Ground (GND)
61, 62, 89, 90
10, 11, 40, 41, Vcc
65, 66, 85, 86
VCCIO
NC2
16 Supply voltage for output drivers, 5V or 3.3V.
1, 2, 12, 13, No Connect
24, 25, 26, 27,
38, 39, 49, 50,
51, 52, 63, 64,
74, 75, 76, 77,
87, 88, 99, 100
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
Table 2-0002A/1024EA
11
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