PDF ispLSI1016EA-125LJ44 Data sheet ( Hoja de datos )

Número de pieza	ispLSI1016EA-125LJ44
Descripción	In-System Programmable High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 1016EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Functionally Compatible with ispLSI 1016E • NEW FEATURES — 100% IEEE 1149.1 Boundary Scan Testable — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (VCCIO Pin) — Open-Drain Output Option • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms A0 A1 D Q A2 D Q Logic A3 Array D Q GLB A4 DQ A5 A6 A7 Global Routing Pool (GRP) B7 B6 B5 B4 B3 B2 B1 B0 CLK Description 0139C/1016EA The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016EA fea- tures 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port. The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the intercon- nect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options. The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (Figure 1). There are a total of 16 GLBs in the ispLSI 1016EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinato- rial or registered. Inputs to the GLB come from the GRP and a dedicated input. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. June 2000 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016ea_01 1 1 page Specifications ispLSI 1016EA Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5ns 1.5V 1.5V See Figure 3 Table 2-0003/1016EA Figure 3. Test Load + 5V Device Output R1 Test Point Output Load Conditions (see Figure 3) R2 CL* TEST CONDITION A Active High B Active Low Active High to Z C at VOH -0.5V Active Low to Z at VOL+0.5V R1 470Ω ∞ 470Ω ∞ R2 390Ω 390Ω 390Ω 390Ω CL 35pF 35pF 35pF 5pF 470Ω 390Ω 5pF Table 2-0004/1016E *CL includes Test Fixture and Probe Capacitance. 0213a DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS VOL Output Low Voltage IOL = 8 mA — — 0.4 V VOH Output High Voltage IOH = -2 mA, VCCIO = 3.0V IOH = -4 mA, VCCIO = 4.75V 2.4 — — V 2.4 — — V IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) — — -10 µA IIH Input or I/O High Leakage Current (VCCIO - 0.2)V ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V — — 10 µA — — 10 µA IIL-PU I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL — — -200 µA IOS1 Output Short Circuit Current VCCIO = 5.0V or 3.3V, VOUT = 0.5V — — -240 mA ICC2, 4, 5 Operating Power Supply Current VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz — 91 — mA 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. Table 2-0007/1016EA 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Unused inputs held at 0.0V. 5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book CD-ROM to estimate maximum ICC. 5 5 Page Specifications ispLSI 1016EA Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 GOE 0/IN 31 PLCC PIN NUMBERS 15, 16, 17, 18, 19, 20, 21, 22, 25, 26, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 41, 42, 43, 44, 3, 4, 5, 6, 7, 8, 9, 10 2 TDI TMS 14 36 TQFP PIN NUMBERS DESCRIPTION 9, 10, 11, 12, 13, 14, 15, 16, 19, 20, 21, 22, 23, 24, 25, 26, 31, 32, 33, 34, 35, 36, 37, 38, 41, 42, 43, 44, 1, 2, 3, 4 Input/Output Pins - These are the general purpose I/O pins used by the logic array. 40 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. 8 Input - Functions as an input pin to load programming data into the device and also used as one of the two control pins for the ispJTAG state machine. 30 Input - Controls the operation of the ISP state machine. TDO 24 18 Output - Functions as an output pin to read serial shift register data. TCK 33 27 Input - Functions as a clock pin for the Serial Shift Register. Y0 Y1/RESET1 11 35 5 Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. 29 This pin performs two functions: Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. GND VCC 1, 23 12, 34 17, 39 6, 28 Ground (GND) VCC VCCIO 13 7 Supply voltage for output drivers, 5V or 3.3V. 1. Pins have dual function capability which is software selectable. Table 2-0002C/1016EA 11 11 Page

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