PDF ispLSI1016E-80LJI Data sheet ( Hoja de datos )

Número de pieza	ispLSI1016E-80LJI
Descripción	In-System Programmable High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 1016E In-System Programmable High Density PLD Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP™) 5V Only — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram A0 A1 D Q A2 D Q Logic A3 Array D Q GLB A4 DQ A5 A6 A7 Global Routing Pool (GRP) B7 B6 B5 B4 B3 B2 B1 B0 CLK Description 0139C1-isp The ispLSI 1016E is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E features 5V in-system programming and in-system diagnostic capabilities. The ispLSI 1016E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. October 1998 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016e_06 1 1 page Specifications ispLSI 1016E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 4 COND. #2 DESCRIPTION1 -125 -100 -80 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 ns tpd2 A 2 Data Prop. Delay, Worst Case Path – 10.0 – 13.0 – 18.5 ns fmax A 3 Clk. Frequency with Int. Feedback3 125 – 100 – 84.0 – MHz fmax (Ext.) – 4 Clk. Frequency with Ext. (Feedback 1 tsu2 + )tco1 100 – 77.0 – 57.0 – MHz fmax (Tog.) – 5 Clk. Frequency, Max. Toggle( 1 twh + )tw1 167 – 125 – 100 – MHz tsu1 – 6 GLB Reg. Setup Time before Clk., 4 PT Bypass 5.0 – 7.0 – 8.5 – ns tco1 A 7 GLB Reg. Clk. to Output Delay, ORP Bypass – 4.5 – 5.0 – 8.0 ns th1 – 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 0.0 – 0.0 – 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clk. 5.5 – 8.0 – 9.5 – ns tco2 – 10 GLB Reg. Clk. to Output Delay – 5.5 – 6.0 – 9.5 ns th2 – 11 GLB Reg. Hold Time after Clk. 0.0 – 0.0 – 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay – 10.0 – 13.5 – 17.0 ns trw1 – 13 Ext. Reset Pulse Duration 5.0 – 6.5 – 10.0 – ns tptoeen B 14 Input to Output Enable – 12.0 – 15.0 – 20.0 ns tptoedis C 15 Input to Output Disable – 12.0 – 15.0 – 20.0 ns tgoeen B 16 Global OE Output Enable – 7.0 – 9.0 – 10.5 ns tgoedis C 17 Global OE Output Disable – 7.0 – 9.0 – 10.5 ns twh – 18 Ext. Sync. Clk. Pulse Duration, High 3.0 – 4.0 – 5.0 – ns twl – 19 Ext. Sync. Clk. Pulse Duration, Low 3.0 – 4.0 – 5.0 – ns tsu3 – 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – 3.5 – 4.5 – ns th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – 0.0 – 0.0 – ns 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions Section. Table 2-0030-16/125,100, 80 5 5 Page Pin Configurations ispLSI 1016E 44-Pin PLCC Pinout Diagram Specifications ispLSI 1016E 6 5 4 3 2 1 44 43 42 41 40 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN 1SDI/IN 0 I/O 0 I/O 1 I/O 2 7 8 9 10 11 12 13 14 15 16 17 ispLSI 1016E Top View 39 I/O 18 38 I/O 17 37 I/O 16 36 MODE/IN 21 35 Y1/RESET 34 VCC 33 SCLK/Y21 32 I/O 15 31 I/O 14 30 I/O 13 29 I/O 12 18 19 20 21 22 23 24 25 26 27 28 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. ispLSI 1016E 44-Pin TQFP Pinout Diagram 0123A-isp1016 44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN 1SDI/IN 0 I/O 0 I/O 1 I/O 2 1 2 3 4 5 6 7 8 9 10 11 ispLSI 1016E Top View 33 I/O 18 32 I/O 17 31 I/O 16 30 MODE/IN 21 29 Y1/RESET 28 VCC 27 SCLK/Y21 26 I/O 15 25 I/O 14 24 I/O 13 23 I/O 12 12 13 14 15 16 17 18 19 20 21 22 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. 0851-16E/TQFP 11 11 Page

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Número de pieza	Descripción	Fabricantes
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ispLSI1016E-80LJI	In-System Programmable High Density PLD	Lattice Semiconductor

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