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ispLSI1016E-100LT44 の電気的特性と機能

ispLSI1016E-100LT44のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable High Density PLD」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispLSI1016E-100LT44
部品説明 In-System Programmable High Density PLD
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispLSI1016E-100LT44 Datasheet, ispLSI1016E-100LT44 PDF,ピン配置, 機能
ispLSI® 1016E
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Device for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
A0
A1 D Q
A2 D Q
Logic
A3 Array D Q GLB
A4
DQ
A5
A6
A7 Global Routing Pool (GRP)
B7
B6
B5
B4
B3
B2
B1
B0
CLK
Description
0139C1-isp
The ispLSI 1016E is a High Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016E features
5V in-system programming and in-system diagnostic
capabilities. The ispLSI 1016E offers non-volatile
reprogrammability of the logic, as well as the interconnect
to provide truly reconfigurable systems. A functional
superset of the ispLSI 1016 architecture, the ispLSI
1016E device adds a new global output enable pin.
The basic unit of logic on the ispLSI 1016E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 1016E device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
October 1998
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1016e_06
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ispLSI1016E-100LT44 pdf, ピン配列
Specifications ispLSI 1016E
Absolute Maximum Ratings 1
Supply Voltage VCC ................................ -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL
VIH
Supply Voltage
Input Low Voltage
Input High Voltage
PARAMETER
Commercial TA = 0°C to + 70°C
Industrial
TA = -40°C to + 85°C
Capacitance (TA=25oC, f=1.0 MHz)
MIN.
4.75
4.5
0
2.0
MAX. UNITS
5.25
V
5.5 V
0.8 V
Vcc+1
V
Table 2-0005/1016E
SYMBOL
PARAMETER
C1 Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
C2 Y0 Clock Capacitance
Data Retention Specifications
TYPICAL
8
UNITS
pf
TEST CONDITIONS
VCC = 5.0V, VPIN = 2.0V
12 pf VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1016E
PARAMETER
Data Retention
Erase/Reprogram Cycles
MINIMUM
20
10000
MAXIMUM
UNITS
Years
Cycles
Table 2-0008/1016E
3


3Pages


ispLSI1016E-100LT44 電子部品, 半導体
Specifications ispLSI 1016E
Internal Timing Parameters1
PARAMETER #2
DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
GRP
tgrp1
tgrp4
tgrp8
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
tgrp16
32 GRP Delay, 16 GLB Loads
GLB
t4ptbpc
t4ptbpr
34 4 Product Term Bypass Path Delay (Combinatorial)
35 4 Product Term Bypass Path Delay (Registered)
t1ptxor
t20ptxor
txoradj
tgbp
36 1 Product Term/XOR Path Delay
37 20 Product Term/XOR Path Delay
38 XOR Adjacent Path Delay 3
39 GLB Register Bypass Delay
tgsu
tgh
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
tgco
42 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
ORP
torp
torpbp
47 ORP Delay
48 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice hard macros.
-125
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
0.3 0.4 0.6
1.8 2.4 3.6
3.0 3.5 4.5
-0.3 -0.4 -0.6
4.0 5.0 7.5
4.0 5.0 7.5
2.2 2.6 3.9
ns
ns
ns
ns
ns
ns
ns
1.8 1.9 2.9
1.9 2.2 3.3
2.1 2.5 3.8
2.4 3.1 4.7
ns
ns
ns
ns
3.9 5.7 8.1
3.9 5.6 7.3
4.4 6.1 7.1
4.4 6.1 8.2
4.4 6.6 8.3
1.0 1.6 1.9
0.2 0.2 -0.6
1.5 2.5 4.3
1.8 1.9 2.9
4.4 6.3 7.0
3.5 5.1 7.2
5.5 7.1 9.7
3.2 3.5 4.8 5.3 6.8 7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.0 1.0 1.5 ns
0.0
0.0
0.0 ns
Table 2-0036-16/125,100, 80
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部品番号部品説明メーカ
ispLSI1016E-100LT44

In-System Programmable High Density PLD

Lattice Semiconductor
Lattice Semiconductor


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