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PDF ISPL1048E-90LT Data sheet ( Hoja de datos )
| Número de pieza | ISPL1048E-90LT | |
| Descripción | High-Density Programmable Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispLSI® 1048E
High-Density Programmable Logic
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispLSI DEVELOPMENT TOOLS
ispVHDL™ Systems
— VHDL/Verilog-HDL/Schematic Design Options
— Functional/Timing/VHDL Simulation Options
ispDS+™ VHDL Synthesis-Optimized Logic Fitter
— Supports Leading Third-Party Design Environments
for Schematic Capture, Synthesis and Timing
Simulation
— Static Timing Analyzer
ispDS™ Software
— Lattice HDL or Boolean Logic Entry
— Functional Simulator and Waveform Viewer
ISP Daisy Chain Download Software
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
A0
A1
A2
A3
Global Routing Pool (GRP)
A4
A5
A6
A7
DQ
DQ
Logic
Array D Q GLB
DQ
D7
D6
D5
D4
D3
D2
D1
D0
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
CLK
Output Routing Pool
0139G1A-isp
Description
The ispLSI 1048E is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E fea-
tures 5V in-system programmability and in-system
diagnostic capabilities. The ispLSI 1048E offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. A
functional superset of the ispLSI 1048 architecture, the
ispLSI 1048E device adds two new global output enable
pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
July 1998
1048E_08
1
1 page  
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-125
-100
-90
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
A
A
A
–
–
–
1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 10.0 ns
2 Data Propagation Delay, Worst Case Path
– 10.0 – 12.5 – 12.5 ns
3 Clock Frequency with Internal Feedback 3
125.0 – 100.0 – 90.9 – MHz
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
91.0
–
71.0
–
71.0
–
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
twl
)
167.0 – 125.0 – 125.0 –
MHz
MHz
6 GLB Reg. Setup Time before Clock,4 PT Bypass 5.5 – 6.5 – 6.5 – ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 4.5 – 6.5 – 6.5 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 – 0.0 – ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
– 9 GLB Reg. Setup Time before Clock
6.5 – 7.5 – 7.5 – ns
– 10 GLB Reg. Clock to Output Delay
– 5.5 – 7.5 – 7.5 ns
– 11 GLB Reg. Hold Time after Clock
0.0 – 0.0 – 0.0 – ns
A 12 Ext. Reset Pin to Output Delay
– 10.0 – 13.5 – 13.5 ns
– 13 Ext. Reset Pulse Duration
5.0 – 6.5 – 6.5 – ns
B 14 Input to Output Enable
– 12.0 – 15.0 – 15.0 ns
C 15 Input to Output Disable
– 12.0 – 15.0 – 15.0 ns
B 16 Global OE Output Enable
– 7.0 – 9.0 – 9.0 ns
C 17 Global OE Output Disable
– 7.0 – 9.0 – 9.0 ns
– 18 External Synchronous Clock Pulse Duration, High 3.0 – 4.0 – 4.0 – ns
– 19 External Synchronous Clock Pulse Duration, Low 3.0 – 4.0 – 4.0 – ns
tsu3
– 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 – 3.5 – 4.0 – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 – 0.0 – 0.0 – ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1048E
5
5 Page 
Specifications ispLSI 1048E
ispLSI 1048E Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#59
#28
I/O Reg Bypass
#22
Input
D Register Q
RST
#23 - 27
Reset
GRP4
#30
GRP Loading
Delay
#29, 31-33
GLB
Feedback
#34 Comb 4 PT Bypass
Reg 4 PT Bypass
#35
20 PT
XOR Delays
#36 - 38
#59
GLB Reg Bypass
#39
GLB Reg
Delay
DQ
RST
#40 - 43
ORP
I/O Cell
ORP Bypass
#48
ORP
Delay
#47
#49, 50
I/O Pin
(Output)
#51, 52
Y1,2,3
Clock
Distribution
#55 - 58
Control RE
PTs OE
#44 - 46 CK
Y0
GOE 0,1
#54
#53
Derivations of tsu, th and tco from the Product Term Clock1
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th = Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
3.5 ns = (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#47 + #49)
10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Derivations of tsu, th and tco from the Clock GLB 1
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
3.4 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)
th = Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
2.2 ns = (0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
9.6 ns = (0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
Table 2-0042/1048E
0491
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISPL1048E-90LT.PDF ] | |
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