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ISPL1048E-100LQ の電気的特性と機能

ISPL1048E-100LQのメーカーはLattice Semiconductorです、この部品の機能は「High-Density Programmable Logic」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISPL1048E-100LQ
部品説明 High-Density Programmable Logic
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ISPL1048E-100LQ Datasheet, ISPL1048E-100LQ PDF,ピン配置, 機能
ispLSI® 1048E
High-Density Programmable Logic
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispLSI DEVELOPMENT TOOLS
ispVHDL™ Systems
— VHDL/Verilog-HDL/Schematic Design Options
— Functional/Timing/VHDL Simulation Options
ispDS+™ VHDL Synthesis-Optimized Logic Fitter
— Supports Leading Third-Party Design Environments
for Schematic Capture, Synthesis and Timing
Simulation
— Static Timing Analyzer
ispDS™ Software
— Lattice HDL or Boolean Logic Entry
— Functional Simulator and Waveform Viewer
ISP Daisy Chain Download Software
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
A0
A1
A2
A3
Global Routing Pool (GRP)
A4
A5
A6
A7
DQ
DQ
Logic
Array D Q GLB
DQ
D7
D6
D5
D4
D3
D2
D1
D0
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
CLK
Output Routing Pool
0139G1A-isp
Description
The ispLSI 1048E is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E fea-
tures 5V in-system programmability and in-system
diagnostic capabilities. The ispLSI 1048E offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. A
functional superset of the ispLSI 1048 architecture, the
ispLSI 1048E device adds two new global output enable
pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
July 1998
1048E_08
1

1 Page





ISPL1048E-100LQ pdf, ピン配列
Specifications ispLSI 1048E
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL
VIH
Supply Voltage
Input Low Voltage
Input High Voltage
PARAMETER
Commercial TA = 0°C to + 70°C
Industrial
TA = -40°C to + 85°C
Capacitance (TA=25oC, f=1.0 MHz)
MIN.
4.75
4.5
0
2.0
MAX. UNITS
5.25
V
5.5 V
0.8 V
Vcc+1
V
Table 2-0005/1048E
SYMBOL
C1
C2
PARAMETER
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
Y0 Clock Capacitance
TYPICAL
8
15
UNITS
pf
pf
TEST CONDITIONS
VCC = 5.0V, VPIN = 2.0V
VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1048E
Data Retention Specifications
PARAMETER
Data Retention
Erase/Reprogram Cycles
MINIMUM
20
10000
MAXIMUM
UNITS
Years
Cycles
Table 2-0008/1048E
3


3Pages


ISPL1048E-100LQ 電子部品, 半導体
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-70 -50
UNITS
MIN. MAX. MIN. MAX.
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
A
A
A
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay, Worst Case Path
3 Clock Frequency with Internal Feedback 3
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
twl
)
6 GLB Reg. Setup Time before Clock,4 PT Bypass
– 15.0 – 20.0
– 18.5 – 24.5
70.0 – 50.0 –
56.0 – 42.0 –
100.0 – 77.0 –
9.0 – 12.0 –
ns
ns
MHz
MHz
MHz
ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 7.0 – 9.5 ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 – ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
– 9 GLB Reg. Setup Time before Clock
– 10 GLB Reg. Clock to Output Delay
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
B 16 Global OE Output Enable
C 17 Global OE Output Disable
– 18 External Synchronous Clock Pulse Duration, High
– 19 External Synchronous Clock Pulse Duration, Low
11.0 – 14.5 –
– 9.0 – 12.0
0.0 – 0.0 –
– 15.0 – 20.5
10.0 – 13.0 –
– 18.0 – 24.0
– 18.0 – 24.0
– 12.0 – 16.0
– 12.0 – 16.0
5.0 – 6.5 –
5.0 – 6.5 –
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu3
– 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
4.0 – 6.5 – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0 – 0.0 – ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/1048E
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ISPL1048E-100LQ

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ISPL1048E-100LQI

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ISPL1048E-100LT

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ISPL1048E-100LTI

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor


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