ispGDX160V-7B208 Datasheet PDF - Lattice Semiconductor
| Part Number | ispGDX160V-7B208 | |
| Description | In-System Programmable 3.3V Generic Digital CrosspointTM | |
| Manufacturers | Lattice Semiconductor | |
| Logo |  |
|
|
There is a preview and ispGDX160V-7B208 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
Preview 1 page No Preview Available !
ispGDXTM160V/VA
In-System Programmable
3.3V Generic Digital CrosspointTM
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
I/O Pins D
ISP
Control
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)*
— Low-Power: 16.5mA Quiescent Icc*
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
Boundary
Scan
Control
Description
I/O Pins B
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins
(40)
— Single Level 4:1 Dynamic Path Selection (Tpd=3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
* “VA” Version Only
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 2000
gdx160va_04
1
|
| |
 
Specifications ispGDX160V/VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX160V/VA, I/O D23
I/O Group A
D21 MUX Out
I/O Group B
D22 MUX Out
I/O Group C
D24 MUX Out
I/O Group D
D25 MUX Out
ispGDX160V/VA I/O Cell
4x4
Crossbar
Switch
S1 S0
.m0
.m1 D23
.m2
.m3
It can be seen from Figure 3 that if the D21 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
The ispGDXV/VA can implement MUXes up to 16 bits
wide in a single level of logic, but care must be taken
when combining adjacent I/O cell outputs with direct
MUX inputs. Any particular combination of adjacent I/O
cells as MUX inputs will dictate what I/O groups (A, B, C
or D) can be routed to the remaining inputs. By properly
choosing the adjacent I/O cells, all of the MUX inputs can
be utilized.
Special Features
Slew Rate Control
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate op-
tions.
Open Drain Control
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX160V/VA)
Data A/ Data B/ Data C/ Data D/
MUXOUT MUXOUT MUXOUT MUXOUT
B20 B22 B21 B19 B18
B21 B23 B22 B20 B19
B22 B24 B23 B21 B20
Reflected B23 B25 B24 B22 B21
I/O Cells D16 D18 D17 D15 D14
D17 D19 D18 D16 D15
D18 D20 D19 D17 D16
D19 D21 D20 D18 D17
D20 D18 D19 D21 D22
D21 D19 D20 D22 D23
D22 D20 D21 D23 D24
Normal D23 D21 D22 D24 D25
I/O Cells
B16 B14 B15 B17 B18
B17 B15 B16 B18 B19
B18 B16 B17 B19 B20
B19 B17 B18 B20 B21
ispGDX160VA New Features
Unique to the ispGDX160VA are user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX160VA uses a VCCIO pin to provide
the 2.5V reference voltage when used. The ispGDX160VA
VCCIO pin occupies the same location as VCC on the
ispGDX160V, allowing drop-in replacement. The
ispGDX160VA offers improved performance by reducing
fanout delays and has PCI compatible drive capability.
Only the ispGDX160VA is available in the fastest (3.5ns)
Commercial speed grade and in -5,-7, and -9ns Industrial
grades in all packages.
The ispGDX160VA has a device ID different from the
ispGDX160V requiring that the latest Lattice download
software be used for programming and verification. Al-
though the ispGDX160VA and ispGDX160V are
functionally equivalent, they are not 100% JEDEC com-
patible. All design files must be recompiled targeting the
ispGDX160VA.
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ispGDX160V-7B208 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ispGDX160V-7B208.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| ispGDX160V-7B208 | The function is In-System Programmable 3.3V Generic Digital CrosspointTM. Lattice Semiconductor | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
ispG
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||