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ispGDX160V-5B272 の電気的特性と機能

ispGDX160V-5B272のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable 3.3V Generic Digital CrosspointTM」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispGDX160V-5B272
部品説明 In-System Programmable 3.3V Generic Digital CrosspointTM
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispGDX160V-5B272 Datasheet, ispGDX160V-5B272 PDF,ピン配置, 機能
ispGDXTM160V/VA
In-System Programmable
3.3V Generic Digital CrosspointTM
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
I/O Pins D
ISP
Control
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)*
— Low-Power: 16.5mA Quiescent Icc*
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
Boundary
Scan
Control
Description
I/O Pins B
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins
(40)
— Single Level 4:1 Dynamic Path Selection (Tpd=3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
* “VA” Version Only
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 2000
gdx160va_04
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ispGDX160V-5B272 pdf, ピン配列
Specifications ispGDX160V/VA
Architecture
The ispGDXV/VA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The program-
mable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI devices, there are no pro-
grammable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch con-
trolled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in a 160 I/O
ispGDXV, each data input can connect to one of 40 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)
Logic 0Logic 1
160 I/O Inputs
I/OCell 0
I/O Cell 159
I/O Cell 1
•••
••
E2CMOS
Programmable
Interconnect
I/O Group A
I/O Group B
I/O Group C
I/O Group D
I/O Cell 158
•••
From MUX Outputs
of 2 Adjacent I/O Cells
N+2
N+1
4x4
Crossbar
Switch
N-1
N-2
To 2 Adjacent
I/O Cells above
4-to-1 MUX
M0
M1
M2
M3
MUX0 MUX1
Bypass Option
Register
or Latch
A
BD
Q
CLK
C
R
Prog. Prog.
Pull-up Bus Hold
(VCCIO) Latch
I/O
Pin
Prog. Open Drain
From MUX Outputs
of 2 Adjacent I/O Cells
To 2 Adjacent
I/O Cells below
CLK_EN Reset
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell 78
I/O Cell 79
80 I/O Cells
••••••
160 Input GRP
Inputs Vertical
Outputs Horizontal
Global
Y0-Y3 Reset
Global
Clocks /
Clock_Enables
•••
I/O Cell 81
80 I/O Cells
I/O Cell 80
ispGDXV/VA architecture enhancements over ispGDX (5V)
3
I/O Cell N


3Pages


ispGDX160V-5B272 電子部品, 半導体
Specifications ispGDX160V/VA
Applications
The ispGDXV/VA Family architecture has been devel-
oped to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices
are targeted for three similar but distinct classes of end-
system applications:
Programmable, Random Signal
Interconnect (PRSI)
This class includes PCB-level programmable signal rout-
ing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of program-
mable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control in-
puts.
Programmable Data Path (PDP)
This application area includes system data path trans-
ceiver, MUX and latch functions. With todays 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of on-boardbus and memory inter-
faces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to inte-
grate these on-board data path functions in an analogous
way to programmable logics solution to control logic
integration. Lattices CPLDs make an ideal control logic
complement to the ispGDXV/VA in-system program-
mable data path devices as shown below.
Figure 4. ispGDXV/VA Complements Lattice CPLDs
Address
Inputs
(from P)
Control
Inputs
(from P)
Data Path
Bus #1
Programmable Switch Replacement (PSR)
Includes solid-state replacement and integration of me-
chanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDXV/VA de-
vices can be driven to HIGH or LOW logic levels to
emulate the traditional device outputs. PSR functions do
not require any input pin connections.
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDXV/VA device will inter-
face with control logic outputs from other components
(such as ispLSI or ispMACH) on the board (which fre-
quently change late in the design process as control logic
is finalized), there must be no restrictions on pin-to-pin
signal routing for this type of application.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the pro-
grammable interconnect is used to define possible signal
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architec-
ture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin re-
routing is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
State Machines
ispLSI/
ispMACH
Device
ISP/JTAG
Buffers / Registers Interface
Control
Outputs
ispGDXV/VA
Device
Decoders
System
Clock(s)
Buffers / Registers
Data Path
Bus #2
Configuration
(Switch)
Outputs
As a result, the ispGDXV/VA architecture has been
defined to support PSR and PRSI applications (including
bidirectional paths) with no restrictions, while PDP appli-
cations (using dynamic MUXing) are supported with a
minimal number of restrictions as described below. In this
way, speed and cost can be optimized and the devices
can still support the system designers needs.
The following diagrams illustrate several ispGDXV/VA
applications.
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部品番号部品説明メーカ
ispGDX160V-5B272

In-System Programmable 3.3V Generic Digital CrosspointTM

Lattice Semiconductor
Lattice Semiconductor


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