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ispGDX160-5Q208 の電気的特性と機能

ispGDX160-5Q208のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable Generic Digital CrosspointTM」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispGDX160-5Q208
部品説明 In-System Programmable Generic Digital CrosspointTM
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispGDX160-5Q208 Datasheet, ispGDX160-5Q208 PDF,ピン配置, 機能
ispGDXTM Family
In-System Programmable
Generic Digital CrosspointTM
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Three Device Options: 80 to 160 Programmable I/O
Pins
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
— PCI Compliant Output Drive
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
Slew Rate Control
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• ispGDX OFFERS THE FOLLOWING ADVANTAGES
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
Programmable Clocks from I/O Pins (from 20 up to
40)
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
I/O Pins D
ISP
Control
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
Boundary
Scan
Control
I/O Pins B
Description
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 4:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
ispgdx_08
1

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ispGDX160-5Q208 pdf, ピン配列
Specifications ispGDX Family
Architecture
The ispGDX architecture is different from traditional PLD
architectures, in keeping with its unique application fo-
cus. The block diagram is shown below. The
programmable interconnect consists of a single Global
Routing Pool (GRP). Unlike ispLSI devices, there are no
programmable logic arrays on the device. Control signals
for OEs, Clocks and MUX Controls must come from
designated sets of I/O pins. The polarity of these signals
can be independently programmed in each I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
The in-system programming process uses either a Bound-
ary Scan based or Lattice ISP protocol. The programming
protocol is selected by the BSCAN/ispEN pin as de-
scribed later.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines called MUX0 and MUX1 as shown in
Figure 1. The four data inputs to the MUX (called MUXA,
MUXB, MUXC and MUXD) come from I/O signals found
in the GRP. Each MUX data input can access one quarter
of the total I/Os. For example, in a 160 I/O ispGDX, each
data input can connect to one of 40 I/O pins. MUX0 and
MUX1 can be driven by designated I/O pins called
MUXsel1 and MUXsel2. Each MUXsel input covers 25%
of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1
can be driven from either MUXsel1 or MUXsel2. The I/O
cell also includes a programmable flow-through latch or
register that can be placed in the input or output path and
bypassed for combinatorial outputs. As shown in Figure
1, when both register/latch control MUXes select the A
path, the register/latch gets its inputs from the 4:1 MUX
and drives the I/O output. When selecting the Bpath,
the register/latch is directly driven by the I/O input while
its output feeds the GRP. The programmable polarity
Clock to the latch or register can be connected to any
I/O in the I/O-Clock set (one-quarter of total I/Os) or to
one of the dedicated clock input pins (Yx). Use of the
dedicated clock inputs gives minimum clock-to-output
delays and minimizes delay variation with fanout. Com-
binatorial output mode may be implemented by a
dedicated architecture bit and bypass MUX. I/O cell
output polarity can be programmed as active high or
active low.
Figure 1. ispGDX I/O Cell and GRP Detail (160 I/O Device)
I/O 0
I/O 1
Logic "1" 160 I/O Inputs
E2CMOS
Programmable
Interconnect
•••
•••
I/O 80
I/O 81
4-to-1 MUX
MUXA
MUXB
MUXC
MUXD
MUX0 MUX1
•••
Bypass Option
Register
A or Latch
BD
Q
CLK
Reset
I/O Cell N
Prog.
Pull-up
C I/O Pin
R
Programmable
Slew Rate
Boundary
Scan Cell
I/O MUX Operation
MUX1 MUX0 DATA INPUT SELECTED
00
MUXA
01
MUXB
11
MUXC
10
MUXD
I/O 78
I/O 79
80 I/O Cells
••••••
160 Input GRP
Inputs Vertical Y0-Y3
Outputs Horizontal Global
Clocks
Global
Reset
I/O 158
I/O 159
80 I/O Cells
3


3Pages


ispGDX160-5Q208 電子部品, 半導体
Specifications ispGDX Family
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the Absolute Maximum Ratingsmay cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL1
VIH1
Supply Voltage
Input Low Voltage
Input High Voltage
1. Typical 100mV of input hysteresis.
PARAMETER
Commercial TA = 0°C to +70°C
MIN.
4.75
0
2.0
MAX.
5.25
0.8
Vcc + 1
UNITS
V
V
V
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C1
C2
PARAMETER
I/O Capacitance
Dedicated Clock Capacitance
TYPICAL
8
10
UNITS
pf
pf
TEST CONDITIONS
VCC = 5.0V, VI/O = 2.0V
VCC = 5.0V, VY= 2.0V
Table 2 - 0006
Erase/Reprogram Specifications
PARAMETER
ispGDX Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
6

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部品番号部品説明メーカ
ispGDX160-5Q208

In-System Programmable Generic Digital CrosspointTM

Lattice Semiconductor
Lattice Semiconductor


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