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PDF ISP1301 Data sheet ( Hoja de datos )
| Número de pieza | ISP1301 | |
| Descripción | Universal Serial Bus On-The-Go transceiver | |
| Fabricantes | NXP Semiconductors | |
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ISP1301
Universal Serial Bus On-The-Go transceiver
Rev. 01 — 14 April 2004
Product data
1. General description
The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go
Supplement to the USB Specification Rev. 1.0a. The ISP1301 can transmit and
receive serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data
rates.
It is ideal for use in portable electronics devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application Specific Integrated Circuits (ASICs),
Programmable Logic Devices (PLDs) and any system chip set (with the USB host or
device function built-in but without the USB physical layer) to interface to the physical
layer of the USB.
The ISP1301 can interface to devices with digital I/O voltages in the range of
1.65 V to 3.6 V.
The ISP1301 is available in HVQFN24 package.
2. Features
s Fully complies with:
x Universal Serial Bus Specification Rev. 2.0
x On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a
x On-The-Go Transceiver Specification (CEA–2011) Rev. 1.0
s Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
s Ideal for system ASICs or chip sets with built-in USB OTG dual-role core
s Supports mini USB analog car kit interface
s Supports various serial data interface protocols; transparent general-purpose
buffer mode allows you to control the direction of data transfer
s Supports data line and VBUS pulsing session request
s Contains Host Negotiation Protocol (HNP) command and status registers
s Supports serial I2C-bus™ interface for OTG status and command controls
s 2.7 V to 4.5 V power supply input range for the ISP1301
s Built-in charge pump regulator outputs 5 V at current greater than 8 mA
s Supports external charge pump
s Supports wide range interfacing I/O voltage (VDD_LGC = 1.65 V to 3.6 V) for digital
control logics
1 page  
Philips Semiconductors
ISP1301
USB OTG transceiver
7.2 Pin description
Table 2: Pin description[1]
Symbol[2] Pin
Type[3]
ADR/PSW 1
I/O
SDA
2
SCL 3
RESET_N 4
INT_N
5
SPEED 6
I/OD
I/OD
I
OD
I
VREG(3V3) 7
SUSPEND 8
P
I
OE_N/
INT_N
9
I/O
VM
VP
RCV
10 O
11 O
12 O
Reset
value
high-Z
high-Z
high-Z
-
high-Z
-
-
-
high-Z
-
-
0
Description
ADR input — sets the least-significant I2C-bus
address bit of the ISP1301; latched-on reset
(including power-on reset)
PSW output — enables or disables the external
charge pump after reset
bidirectional; push-pull input; three-state output
serial I2C-bus data input and output
bidirectional; push-pull input; open-drain output
serial I2C-bus clock input and output
bidirectional; push-pull input; open-drain output
asynchronous reset; active LOW
push-pull input
interrupt output; active LOW
open-drain output
speed selection input for the ATX; effective when
bit SPD_SUSP_CTRL = 0:
• LOW: low-speed
• HIGH: full-speed.
push-pull input
output of the internal voltage regulator; an
external decoupling capacitor of 0.1 µF is
required
suspend selection input for ATX; effective when
bit SPD_SUSP_CTRL = 0:
• LOW: normal operating
• HIGH: suspend.
push-pull input
OE_N input — enable driving DP and DM when
in the USB mode
INT_N output — interrupt (push pull) when
suspended and bit OE_INT_EN = 1
bidirectional; push-pull input; three-state output
single-ended DM receiver output
push-pull output
single-ended DP receiver output
push-pull output
differential receiver output; reflects the
differential value of DP and DM
push-pull output
9397 750 11355
Product data
Rev. 01 — 14 April 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 46
5 Page 
Philips Semiconductors
ISP1301
USB OTG transceiver
8.9.10 VBAT
This pin is an input and supplies power to the ISP1301. The ISP1301 operates when
VBAT is between 2.7 V and 4.5 V.
8.9.11 C1 and C2
The C1 and C2 pins are for connecting the flying capacitor of the charge pump. The
output current capacity of the charge pump depends on the value of the capacitor.
For maximum efficiency, place capacitors as close as possible to the pins.
C1
ISP1301
C2
VBUS
004aaa278
Cext
IL
9397 750 11355
Product data
Fig 5. Charge pump capacitor.
Table 3:
Cext
47 nF
100 nF
Recommended charge pump capacitor value
IL (max)[1]
8 mA
18 mA[2]
[1] For output voltage VBUS > 4.7 V (bit VBUS_VLD = 1).
[2] For VBAT = 3.0 V to 4.5 V.
8.9.12 VDD_LGC
This pin is an input and sets logic thresholds. It also powers the pads of the following
logic pins:
• ADR/PSW
• DAT/VP, SE0/VM and RCV
• VM and VP
• INT_N
• OE_N/INT_N
• RESET_N
• SPEED
• SUSPEND
• SCL and SDA.
8.9.13 AGND, CGND and DGND
AGND, CGND and DGND are ground pins for analog, charge pump and digital
circuits, respectively. These pins can be connected separately or together depending
on the system performance requirements.
Rev. 01 — 14 April 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 46
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