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PDF ISP1183BS Data sheet ( Hoja de datos )
| Número de pieza | ISP1183BS | |
| Descripción | Low-power Universal Serial Bus interface device with DMA | |
| Fabricantes | NXP Semiconductors | |
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ISP1183
Low-power Universal Serial Bus interface device with DMA
Rev. 01 — 24 February 2004
Product data
1. General description
The ISP1183 is a Universal Serial Bus (USB) interface device that complies with
Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed
(12 Mbit/s). It provides full-speed USB communication capacity to microcontroller or
microprocessor-based systems. The ISP1183 communicates with the system’s
microcontroller or microprocessor through a fast general-purpose parallel interface.
The ISP1183 supports fully autonomous, multiconfigurable Direct Memory Access
(DMA) operation.
The modular approach to implementing a USB interface device allows designer to
select the optimum system microcontroller from the wide variety available. The ability
to reuse existing architecture and firmware investments shortens development time,
eliminates risks and reduces costs. The result is fast and efficient development of the
most cost-effective USB peripheral solution.
The ISP1183 supports I/O voltage range of 1.65 V to 3.6 V enabling it to be directly
interfaced to battery-operated devices, such as mobile phones. The ISP1183 is
ideally suited for battery-operated (low power) application in many portable
peripherals such as mobile phones, Personal Digital Assistants (PDAs) and MP3
players. This device can be used in bus-powered or hybrid-powered applications.
Also, more number of endpoints in the ISP1183 enable the device to be used in
applications such as multifunctional printers, other than standard applications such
as printers, communication devices, scanners, external mass storage devices and
digital still cameras.
2. Features
s Complies with Universal Serial Bus Specification Rev. 2.0 and most Device Class
specifications
s Complies with ACPI™, OnNow™ and USB power management requirements
s Supports data transfer at full-speed (12 Mbit/s)
s High performance USB interface device with integrated Serial Interface Engine
(SIE), FIFO memory, transceiver, and 3.3 V voltage regulator
s High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface
s Fully autonomous and multiconfiguration DMA operation
s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints
s Integrated physical 2462 bytes of multiconfiguration FIFO memory
s Endpoints with double buffering to increase throughput and ease real-time data
transfer
s Seamless interface with most microcontrollers and microprocessors
1 page  
Philips Semiconductors
7. Pinning information
7.1 Pinning
ISP1183
Low-power USB interface device with DMA
9397 750 11804
Product data
VBUS
XTAL2
8
7
XTAL1
DGND
6
5
RD_N 4
WR_N
CS_N
3
2
INT_N 1
GND (exposed die pad)
ISP1183BS
terminal 1
17 A0
18 VDD(I/O)
19 DATA0
20 DATA1
21 VDD
22 DGND
23 DATA2
24 DATA3
Bottom view
004aaa433
Fig 2. Pin configuration HVQFN32.
7.2 Pin description
Table 2: Pin description
Symbol[1]
Pin
Type Description
INT_N
1 O interrupt output; active LOW
3.3 V tolerant I/O pad
CS_N
2 I chip select input
3.3 V tolerant I/O pad
WR_N 3 I write strobe input
3.3 V tolerant I/O pad
RD_N
4 I read strobe input
3.3 V tolerant I/O pad
DGND 5 - digital ground supply
XTAL1 6 I crystal oscillator input (6 MHz); connect a fundamental
parallel-resonant crystal or an external clock source (leave
pin XTAL2 unconnected)
XTAL2 7 O crystal oscillator output (6 MHz); connect a fundamental
parallel-resonant crystal; leave this pin open when using an
external clock source on pin XTAL1
Rev. 01 — 24 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 62
5 Page 
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
XTAL2
6
ISP1183
XTAL1
7
18 pF
6 MHz
18 pF
004aaa294
Fig 5. Typical oscillator circuit.
The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL.
In the suspend state, the crystal oscillator and the PLL are switched off to save
power. The oscillator operation is controlled by using bit CLKRUN in the Hardware
Configuration register. CLKRUN switches the oscillator on and off.
8.13 Power-on reset
The ISP1183 has an internal power-on reset (POR) circuit. The clock signal normally
requires 3 ms to 4 ms to stabilize.
The triggering voltage of the POR circuit is 0.5 V nominal. A POR is automatically
generated when VDD(I/O) goes below the trigger voltage for a duration longer than
50 µs.
VDD(I/O)
0.5 V
POR
≤ 350 µs
2 ms
0V
t1: clock is running
t2: registers are accessible
Fig 6. POR timing.
t1
t2
004aaa390
9397 750 11804
Product data
POR
EXTERNAL CLOCK
A
Stable external clock available at A.
Fig 7. Clock with respect to the external POR.
Rev. 01 — 24 February 2004
004aaa365
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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