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PDF ISP1161BD Data sheet ( Hoja de datos )
| Número de pieza | ISP1161BD | |
| Descripción | Full-speed Universal Serial Bus single-chip host and device controller | |
| Fabricantes | NXP Semiconductors | |
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ISP1161
Full-speed Universal Serial Bus single-chip host and device
controller
Rev. 01 — 3 July 2001
Product data
1. General description
The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and
Device Controller (DC) which complies with Universal Serial Bus Specification
Rev 1.1. These two USB controllers, the HC and the DC, share the same
microprocessor bus interface. They have the same data bus, but different I/O
locations. They also have separate interrupt request output pins, separate DMA
channels that include separate DMA request output pins and DMA acknowledge
input pins. This makes it possible for a microprocessor to control both the USB HC
and the USB DC at the same time.
ISP1161 provides two downstream ports for the USB HC and one upstream port for
the USB DC. Each downstream port has its own overcurrent (OC) detection input pin
and power supply switching control output pin. The upstream port has its own VBUS
detection input pin. ISP1161 also provides separate wakeup input pins and
suspended status output pins for the USB HC and the USB DC, respectively. This
makes power management flexible. The downstream ports for the HC can be
connected with any USB compliant USB devices and USB hubs that have USB
upstream ports. The upstream port for the DC can be connected to any USB
compliant USB host and USB hubs that have USB downstream ports.
c The DC is compliant with most device class specifications such as Imaging Class,
c
Mass Storage Devices, Communication Devices, Printing Devices and Human
Interface Devices.
ISP1161 is well suited for embedded systems and portable devices that require a
USB host only, a USB device only, or a combined and configurable USB host and
USB device capabilities. ISP1161 brings high flexibility to the systems that have it
built-in. For example, a system that has ISP1161 built-in allows it not only to be
connected to a PC or USB hub that has a USB downstream port, but also to be
connected to a device that has a USB upstream port such as a USB printer, USB
camera, USB keyboard, USB mouse, among others. ISP1161 enables peer-to-peer
connectivity between embedded systems. An interesting application example is to
connect a ISP1161 HC with a ISP1161 DC.
Let us see an example of ISP1161 being used in a Digital Still Camera (DSC) design.
Figure 1 shows ISP1161 being used as a USB DC. Figure 2 shows ISP1161 being
used as a USB HC. Figure 3 shows ISP1161 being used as a USB HC and a USB
DC at the same time.
1 page  
to/ from
microprocessor
H_WAKEUP
H_SUSPEND
NDP_SEL
D0 to D15
RD
CS
WR
A1
A0
DACK2
DACK1
EOT
DREQ2
DREQ1
INT2
INT1
16
40
42
33
2 to 7,
9 to 14,
16, 17,
63, 64
22
21
23
60
59
28
27
34
26
25
30
29
HOST/
DEVICE
AUTOMUX
ISP1161
HOST BUS
INTERFACE
DEVICE BUS
INTERFACE
D_WAKEUP
D_SUSPEND
RESET
37
36
32
POWER-ON
RESET
internal
reset
VCC
56
VOLTAGE
3.3 V
REGULATOR
internal
supply
1, 8, 15, 18,
35, 45, 62
57
58 24 19
7
DGND
Vreg (3.3)
AGND
Vhold1
Vhold2
Fig 4. Block diagram.
HOST CONTROLLER
ALT RAM
ITL0
ITL1
(PING RAM) (PONG RAM)
6 MHz
XTAL2
44
XTAL1
43
POWER
SWITCHING
OVERCURRENT
DETECTION
PHILIPS SLAVE
HOST CONTROLLER
Host bus
Device bus
DEVICE
CONTROLLER
CLOCK
RECOVERY
PLL
CLOCK
RECOVERY
USB
TRANSCEIVER
USB
TRANSCEIVER
4×
15 kΩ
GND
USB
TRANSCEIVER
46
47
54
55
50
51
52
53
39
48
49
PING
RAM
PONG
RAM
DEVICE
CONTROLLER
GoodLink
38
GL
SoftConnect
1.5 kΩ
PROGRAMMABLE
DIVIDER
41
CLKOUT
3.3 V
61, 20
2
n.c.
MGT929
H_PSW1
H_PSW2
H_OC1
H_OC2
H_DM1
H_DP1
H_DM2
H_DP2
USB bus
downstream
ports
D_VBUS
D_D M
D_D P
USB bus
upstream
port
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5 Page 
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
7. Functional description
7.1 PLL clock multiplier
A 6 to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external
components are required for the operation of the PLL.
7.2 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using a 4× over-sampling principle. It is able to track jitter and frequency drift as
specified by the USB Specification Rev. 1.1.
7.3 Analog transceivers
Three sets of transceiver are embedded in the chip: two are used for downstream
ports with USB connector type A; one is used for upstream port with USB connector
type B.The integrated transceivers are compliant with the Universal Serial Bus
Specification Rev 1.1. They interface directly with the USB connectors and cables
through external termination resistors.
7.4 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel/serial conversion, bit (de)stuffing, CRC
checking/generation, Packet IDentifier (PID) verification/generation, address
recognition, handshake evaluation/generation. There are separate SIE in both the HC
and the DC.
7.5 SoftConnect (in DC)
The connection to the USB is accomplished by bringing D+ (for high-speed USB
devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1161 the 1.5 kΩ pull-up
resistor is integrated on-chip and is not connected to VCC by default. The connection
is established through a command sent by the external/system microcontroller. This
allows the system microcontroller to complete its initialization sequence before
deciding to establish connection with the USB. Re-initialization of the USB connection
can also be performed without disconnecting the cable.
The ISP1161 DC will check for USB VBUS availability before the connection can be
established. VBUS sensing is provided through pin D_VBUS.
Remark: Note that the tolerance of the internal resistors is 25%. This is higher than
the 5% tolerance specified by the USB specification. However, the overall VSE voltage
specification for the connection can still be met with a good margin. The decision to
make use of this feature lies with the USB equipment designer.
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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