|
|
PDF ISP1160BD Data sheet ( Hoja de datos )
| Número de pieza | ISP1160BD | |
| Descripción | Embedded Universal Serial Bus Host Controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISP1160BD (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
ISP1160
Embedded Universal Serial Bus Host Controller
Rev. 04 — 04 July 2003
Product data
1. General description
The ISP1160 is an embedded Universal Serial Bus (USB) Host Controller (HC) that
complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at
full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1160 provides two
downstream ports. Each downstream port has an overcurrent (OC) detection input
pin and power supply switching control output pin. The downstream ports for the HC
can be connected with any USB compliant USB devices and USB hubs that have
USB upstream ports.
The ISP1160 is well suited for embedded systems and portable devices that require a
USB host. The ISP1160 brings high flexibility to the systems that have it built-in. For
example, a system that has the ISP1160 built-in allows it to be connected to a device
that has a USB upstream port, such as a USB printer, USB camera, USB keyboard,
USB mouse, among others.
2. Features
s Complies with Universal Serial Bus Specification Rev. 2.0
s Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
s Adapted from Open Host Controller Interface Specification for USB Release 1.0a
s Selectable one or two downstream ports for HC
s High-speed parallel interface to most of the generic microprocessors and
Reduced Instruction Set Computer (RISC) processors such as:
x Hitachi® SuperH™ SH-3 and SH-4
x MIPS-based™ RISC
x ARM7™, ARM9™, and StrongARM®
s Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC
s Supports single-cycle and burst mode DMA operations
s Built-in FIFO buffer RAM for the HC (4 kbytes)
s Endpoints with double buffering to increase throughput and ease real-time data
transfer for isochronous (ISO) transactions
s 6 MHz crystal oscillator with integrated PLL for low EMI
s Built-in software selectable internal 15 kΩ pull-down resistors for HC downstream
ports
s Dedicated pins for suspend sensing output and wake-up control input for flexible
applications
s Operation at either +5 V or +3.3 V power supply voltage
s Operating temperature range from −40 °C to +85 °C
s Available in two LQFP64 packages (SOT314-2 and SOT414-1).
1 page  
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Table 2: Pin description for LQFP64…continued
Symbol[1]
Pin Type Description
D5
5 I/O
bit 5 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D6
6 I/O
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D7
7 I/O
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
8-
digital ground
D8
9 I/O
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D9
10 I/O
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D10
11 I/O
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D11
12 I/O
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D12
13 I/O
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D13
14 I/O
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
15 -
digital ground
D14
16 I/O
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D15
17 I/O
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
18 -
digital ground
VHOLD1
19 -
voltage holding pin 1; internally connected to the VREG(3V3)
and VHOLD2 pins. When VCC is connected to 5 V, this pin
will output 3.3 V, hence do not connect it to 5 V. When VCC
is connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
n.c.
20 -
no connection; leave this pin open
CS_N
21 I
chip select input
RD_N
22 I
read strobe input
WR_N
23 I
write strobe input
VHOLD2
24 -
voltage holding pin 2; internally connected to the VREG(3V3)
and VHOLD1 pins. When VCC is connected to 5 V, this pin
will output 3.3 V, hence do not connect it to 5 V. When VCC
is connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
DREQ
25 O
HC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1160 wants to start a
DMA transfer; see Section 10.4.1
n.c.
26 -
no connection; leave this pin open
9397 750 11371
Product data
Rev. 04 — 04 July 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 88
5 Page 
Philips Semiconductors
ISP1160
Embedded USB Host Controller
16-bit register access cycle
write command
(16 bits)
Fig 6. 16-bit register access cycle.
read/write data
(16 bits)
t
MGT937
Most of the ISP1160’s internal control registers are 16-bit wide. Some of the internal
control registers, however, are 32-bit wide. Figure 7 shows how the ISP1160’s 32-bit
internal control register is accessed. The complete cycle of accessing a 32-bit
register consists of a command phase followed by two data phases. In the two data
phases, the microprocessor first reads or writes the lower 16-bit data, followed by the
upper 16-bit data.
32-bit register access cycle
write command
(16 bits)
read/write data
(lower 16 bits)
Fig 7. 32-bit register access cycle.
read/write data
(upper 16 bits)
t
MGT938
To further describe the complete access cycles of the internal control registers, the
status of some pins of the microprocessor bus interface are shown in Figure 8.
Signals
CS_N
A0
RD _ N ,
WR_N
data bus
Valid status
0
1
RD_N = 1,
WR_N = 0
Command code
Valid status
0
0
RD_N = 0 (read) or
WR_N = 0 (write)
Register data
(lower word)
Fig 8. Accessing HC control registers.
Valid status
0
0
RD_N = 0 (read) or
WR_N = 0 (write)
Register data
(upper word)
004aaa370
8.4 FIFO buffer RAM access by PIO mode
Since the ISP1160’s internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal
FIFO buffer RAM is similar to accessing the internal control registers in multiple data
phases.
9397 750 11371
Product data
Rev. 04 — 04 July 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 88
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISP1160BD.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISP1160BD | Embedded Universal Serial Bus Host Controller | NXP Semiconductors |
| ISP1160BM | Embedded Universal Serial Bus Host Controller | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |