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ISL9N318AD3ST PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 ISL9N318AD3ST
部品説明 N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 



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ISL9N318AD3ST Datasheet, ISL9N318AD3ST PDF,ピン配置, 機能
February 2002
ISL9N318AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
Features
• Fast switching
• rDS(ON) = 0.014(Typ), VGS = 10V
• rDS(ON) = 0.024(Typ), VGS = 4.5V
• Qg (Typ) = 18nC, VGS = 5V
• Qgd (Typ) = 3.4nC
• CISS (Typ) = 900pF
DRAIN (FLANGE)
GATE
SOURCE
TO-252
D
G
S
MOSFET Maximum Ratings TA=25°C unless otherwise noted
Symbol
VDSS
VGS
ID
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V)
Continuous (TC = 25oC, VGS = 10V, RθJA= 52oC/W)
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Ratings
30
±20
30
21
9
Figure 4
55
.37
-55 to 175
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
2.73
100
52
Package Marking and Ordering Information
Device Marking
N318AD
Device
ISL9N318AD3ST
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Units
V
V
A
A
A
A
W
W/oC
oC
oC/W
oC/W
oC/W
Quantity
2500 units
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002

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ISL9N318AD3ST

N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs

Fairchild Semiconductor
Fairchild Semiconductor

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