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ISL9N307AD3STのメーカーはFairchild Semiconductorです、この部品の機能は「N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs」です。 |
部品番号 | ISL9N307AD3ST |
| |
部品説明 | N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとISL9N307AD3STダウンロード(pdfファイル)リンクがあります。 Total 11 pages
February 2002
ISL9N307AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
Features
• Fast switching
• rDS(ON) = 0.006Ω (Typ), VGS = 10V
• rDS(ON) = 0.010Ω (Typ), VGS = 4.5V
• Qg (Typ) = 28nC, VGS = 5V
• Qgd (Typ) = 10nC
• CISS (Typ) = 3000pF
DRAIN (FLANGE)
GATE
SOURCE
TO-252
D
G
S
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
VGS
ID
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V)
Continuous (TC = 25oC, VGS = 10V, RθJA = 52oC/W)
Pulsed
PD
Power dissipation
Derate above 25oC
Ratings
30
±20
50
50
15
Figure 4
100
0.67
Units
V
V
A
A
A
A
W
W/oC
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
Package Marking and Ordering Information
Device Marking
N307AD
Device
ISL9N307AD3ST
Package
TO-252AA
Reel Size
330mm
1.36
100
52
Tape Width
16mm
oC/W
oC/W
oC/W
Quantity
2500 units
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
1 Page Typical Characteristic
1.2 60
1.0
VGS = 10V
0.8 40
VGS = 4.5V
0.6
0.4 20
0.2
0
0 25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
0
25
50 75 100 125 150
TC, CASE TEMPERATURE (oC)
175
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
0.1
PDM
0.01
10-5
SINGLE PULSE
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-4
10-3
10-2
10-1
100
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
101
2000
1000
VGS = 10V
100
40
10-5
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
Figure 4. Peak Current Capability
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
175 - TC
150
100 101
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
3Pages Test Circuits and Waveforms (Continued)
VGS
Ig(REF)
VDS
RL
DUT
+
VDD
-
Figure 17. Gate Charge Test Circuit
VDD
VGS
VDS
Qg(TOT)
Qg(5)
VGS = 5V
VGS = 10V
VGS = 1V
0 Qg(TH)
Qgs
Ig(REF)
0
Qgd
Figure 18. Gate Charge Waveforms
VDS
RL
VGS
RGS
DUT
+
VDD
-
VGS
Figure 19. Switching Time Test Circuit
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
10%
VGS
10%
0
50%
PULSE WIDTH
90%
50%
Figure 20. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
6 Page | |||
ページ | 合計 : 11 ページ | ||
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部品番号 | 部品説明 | メーカ |
ISL9N307AD3ST | N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs | Fairchild Semiconductor |