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PDF ISL6614A Data sheet ( Hoja de datos )

Número de pieza ISL6614A
Descripción Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP
Fabricantes Intersil Corporation 
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®
Data Sheet
June 2004
ISL6614A
FN9160
Dual Advanced Synchronous Rectified
Buck MOSFET Drivers with Pre-POR OVP
The ISL6614A integrates two ISL6613A MOSFET drivers and
is specifically designed to drive two Channel MOSFETs in a
synchronous rectified buck converter topology. These drivers
combined with HIP63xx or ISL65xx Multi-Phase Buck PWM
controllers and N-Channel MOSFETs form complete core-
voltage regulator solutions for advanced microprocessors.
The ISL6614A drives both the upper and lower gates
simultaneously over a range from 5V to 12V. This drive-
voltage provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during startup.
The ISL6614A also features a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6614ACB
0 to 85 14 Ld SOIC
M14.15
ISL6614ACB-T 14 Ld SOIC Tape and Reel
ISL6614ACR
0 to 85 16 Ld 4x4 QFN
L16.4x4
ISL6614ACR-T 16 Ld 4x4 QFN Tape and Reel
ISL6614ACBZ *
0 to 85 14 Ld SOIC (Pb-Free) M14.15
ISL6614ACBZ-T * 14 Ld SOIC Tape and Reel (Pb-Free)
ISL6614ACRZ *
0 to 85 16 Ld 4x4 QFN (Pb-Free) L16.4x4
ISL6614ACRZ-T * 16 Ld 4x4 QFN Tape and Reel (Pb-Free)
* Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J Std-020B.
Contact the factory for availability.
Features
• Pin-to-pin Compatible with HIP6602 SOIC family
• Quad N-Channel MOSFET Drives for Two Synchronous
Rectified Bridges
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Available
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC-DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief 400 and 417 for Power Train Design,
Layout Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6614A pdf
ISL6614A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT
tFU
tFL
tPDHU
tPDHL
tPDLU
tPDLL
tPDTS
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
-
-
-
-
-
-
-
Upper Drive Source Current (Note 4)
IU_SOURCE VPVCC = 12V, 3nF Load
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
Upper Drive Sink Current (Note 4)
IU_SINK VPVCC = 12V, 3nF Load
Upper Drive Transition Sink Impedance (Note 3) RU_SINK_TR
Upper Drive DC Sink Impedance
RU_SINK_DC 150mA Source Current
Lower Drive Source Current (Note 4)
IL_SOURCE VPVCC = 12V, 3nF Load
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
Lower Drive Sink Current (Note 4)
IL_SINK VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK 150mA Sink Current
NOTE:
4. Guaranteed by design. Not 100% tested in production.
-
1.25
-
-
0.9
-
0.85
-
0.60
TYP
18
12
10
10
10
10
10
1.25
2.0
2
1.3
1.65
2
1.25
3
0.80
MAX
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
-A
3.0
-A
2.2
3.0
-A
2.2
-A
1.35
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ISL6614A arduino
ISL6614A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
µα
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1 0.0040 0.0098 0.10 0.25
-
B 0.013 0.020 0.33 0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.3367 0.3444 8.55
8.75
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC 1.27 BSC -
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L 0.016 0.050 0.40 1.27
6
N 14
14 7
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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