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PDF ISL6569 Data sheet ( Hoja de datos )
| Número de pieza | ISL6569 | |
| Descripción | Multi-Phase PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
October 2003
ISL6569
FN9085.5
Multi-Phase PWM Controller
The ISL6569 provides core-voltage regulation by driving two
interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6569 uses cost and space-saving rDS(ON) sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The reference and amplifiers are trimmed to ensure
a system accuracy of ± 1% over temperature.
Outstanding features of this controller IC include
Dynamic VIDTM technology allowing seamless on-the-fly VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on VIN, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. #
ISL6569CB
0 to 70 24 Ld SOIC M24.3
ISL6569CB-T
24 Lead SOIC Tape and Reel
ISL6569CR
0 to 70 32 Ld 5x5 QFN L32.5x5
ISL6569CR-T
32 Lead 5x5 QFN Tape and Reel
Features
• Multi-Phase Power Conversion
- 2 Phase Operation
• Active Channel Current Balancing
• Precision rDS(ON) Current Sharing
- Lossless
- Low Cost
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
- ± 1% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VIDTM Technology
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 2MHz)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
Dynamic VID™ is a trademark of Intersil Americas Inc.
1 page  
ISL6569
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3kV
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . .
63
N/A
QFN Package (Note 2). . . . . . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
θJC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0o C to 70oC. Unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply
Shutdown Supply
SHUNT REGULATOR
VCC Voltage
VCC Sink Current
POWER-ON RESET AND ENABLE
VCC = 5VDC; EN = 5VDC; RT = 100kΩ ±1%
VCC = 5VDC; EN = 0VDC; RT = 100kΩ ±1%
VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ
VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ
8.0 10.8 14.0 mA
8.0 10.3 13.0 mA
5.63 5.8 5.97 V
15 20 25 mA
POR Threshold
VCC Rising
4.25 4.35 4.50 V
VCC Falling
3.75 3.85 4.00 V
ENABLE Threshold
EN Rising
1.205 1.23 1.255 V
Hysteresis
86 92 98 mV
REFERENCE VOLTAGE AND DAC
Reference Voltage
0.792 0.8 0.808 V
System Accuracy
VID on Fly Step Size
VID Pull Up
(Note 3)
RT = 100kΩ
-1 - 1 %VID
- 25 - mV
- -20 -
µA
VID Input Low Level
- - 0.8 V
VID Input High Level
- 1.36 1.6
V
PIN-ADJUSTABLE OFFSET
OFS Current
- 100 -
µA
Offset Accuracy
ROFS = 5.00kΩ ±1%
47.0 50.0 53.0 mV
OSCILLATOR
Accuracy
-10 - 10 %
Adjustment Range
0.08 -
1.0 MHz
Disable Voltage
Sawtooth Amplitude
IFS/DIS = 1mA
0.8 1.0 1.2
- 1.37 -
V
V
Max Duty Cycle
- 75 -
%
5
5 Page 
ISL6569
EXTERNAL CIRCUIT
RC
CC
COMP
FB
RFB
+
VDROOP
-
IOUT
VDIFF
ISL6569 INTERNAL CIRCUIT
ERROR AMPLIFIER
-
IAVG
+
+
VCOMP
REFERENCE
VOLTAGE
VOUT
REMOTE
SENSE
POINTS GND
VSEN
RGND
ROFS
OFS
+
VOFS
-
+
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
x0.1
100µA
OFFSET
VOLTAGE
FIGURE 6. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
Most multi-phase controllers simply have the output voltage
fed back to the inverting input of the error amplifier through a
resistor. The ISL6569 features an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
amplifier output, VDIFF, is then tied through an external
resistor to the inverting input of the error amplifier.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20µA pull-up to an internal 2.5V
source for use with open-drain outputs. External pull-up
resistors or active-high output stages can augment the pull-
up current sources, but a slight accuracy error can occur if
they are pulled above 2.9V. The DAC-selected reference
voltage is connected to the non-inverting input of the error
amplifier.
The ISL6569 features a second non-inverting input to the
error amplifier which allows the user to directly offset the
DAC reference voltage in the positive direction only. The
offset voltage is created by an internal current source which
feeds out the OFS pin into a user selected external resistor
to ground. The resulting voltage across the resistor, VOFS, is
internally divided down by ten to create the offset voltage.
This method of offsetting the DAC voltage is more accurate
than external methods of level-shifting the FB pin.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4
VID3 VID2 VID1 VID0
DAC
0 0 0 0 0 1.550
0 0 0 0 1 1.525
0 0 0 1 0 1.500
0 0 0 1 1 1.475
0 0 1 0 0 1.450
0 0 1 0 1 1.425
0 0 1 1 0 1.400
0 0 1 1 1 1.375
0 1 0 0 0 1.350
0 1 0 0 1 1.325
0 1 0 1 0 1.300
0 1 0 1 1 1.275
0 1 1 0 0 1.250
0 1 1 0 1 1.225
0 1 1 1 0 1.200
0 1 1 1 1 1.175
1 0 0 0 0 1.150
1 0 0 0 1 1.125
1 0 0 1 0 1.100
1 0 0 1 1 1.075
1 0 1 0 0 1.050
1 0 1 0 1 1.025
1 0 1 1 0 1.000
1 0 1 1 1 0.975
1 1 0 0 0 0.950
1 1 0 0 1 0.925
1 1 0 1 0 0.900
1 1 0 1 1 0.875
1 1 1 0 0 0.850
1 1 1 0 1 0.825
1 1 1 1 0 0.800
1 1 1 1 1 Shutdown
The integrating compensation network shown in Figure 6
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remote-
sense and error amplifiers. Intersil specifies the guaranteed
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ISL6569.PDF ] | |
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