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PDF ISL6565 Data sheet ( Hoja de datos )
| Número de pieza | ISL6565 | |
| Descripción | Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
PRELIMINARY
Data Sheet
ISL6565A, ISL6565B
December 2003
FN9135
Multi-Phase PWM Controller with
Precision rDS(ON) or DCR Current Sensing
for VR10.X Application
The ISL6565A, ISL6565B controls microprocessor core
voltage regulation by driving up to 3 synchronous-rectified
buck channels in parallel. Multi-phase buck converter
architecture uses interleaved timing to multiply channel
ripple frequency and reduce input and output ripple currents.
The difference between the ISL6565A and the ISL6565B is
that the ISL6565A utilizes rDS(ON) current sensing, while the
ISL6565B utilizes DCR current sensing for each phase.
These cost and space saving methods of current sensing
are used for adaptive voltage positioning (droop), channel-
current balancing, and over-current protection. To ensure
the accuracy of droop, a programmable internal temperature
compensation function is implemented to compensate the
effect of rDS(ON) and DCR temperature sensitivity.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds is eliminated using the remote-sense
amplifier. The precision threshold-sensitive enable input is
available to accurately coordinate the start up of the
ISL6565A, ISL6565B with Intersil MOSFET driver ICs.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6565ACB
0 to 105 28 Ld SOIC
ISL6565ACR
0 to 105 28 Ld 5x5 QFN
ISL6565ACV
0 to 105 28 Ld TSSOP
ISL6565BCB
0 to 105 28 Ld SOIC
ISL6565BCR
0 to 105 28 Ld 5x5 QFN
ISL6565BCV
0 to 105 28 Ld TSSOP
PKG. DWG. #
M28.3
L28.5x5
M28.173
M28.3
L28.5x5
M28.173
Features
• Multi-Phase Power Conversion
- 2 or 3 Phase Operation
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Temperature and Life
- Adjustable Reference-Voltage Offset
• Precision rDS(ON) or DCR Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Low-Cost, Lossless Current Sensing
• Input Voltage: 12V or 5V Bias
• Microprocessor Voltage Identification Input
- Dynamic VID® Technology
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
• Threshold Enable Function for Precision Sequencing
• Over Current Protection
• Over-Voltage Protection
• Digital Soft Start
• Operation Frequency up to 1.5MHz per Phase
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Dynamic VID® is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Application - ISL6565A
ISL6565A, ISL6565B
+5V
FB COMP VCC
VDIFF
VSEN
RGND
TCOMP
PGOOD
OVP
REF
ISL6565A
VID4
PWM1
VID3
ISEN1
VID2
VID1
PWM2
ISEN2
VID0
VID12.5
PWM3
ISEN3
OFS
FS
GND ENLL
RT
NC
EN
+12V
VID_PGOOD
+5V
VCC
EN
BOOT
UGATE
PHASE
ISL6605
PWM LGATE
GND
+5V
VCC
EN
BOOT
UGATE
PHASE
ISL6605
PWM LGATE
GND
+5V
VCC
EN
BOOT
UGATE
PHASE
ISL6605
PWM LGATE
GND
VIN
VIN
VIN
µP
LOAD
5
5 Page 
ISL6565A, ISL6565B
Figures 19 and 20 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6565A, ISL6565B is three. One switching cycle is defined
as the time between PWM1 pulse termination signals. The
pulse termination signal is the internally generated clock
signal that triggers the falling edge of PWM1. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the channel-1
MOSFET driver to turn off the channel-1 upper MOSFET
and turn on the channel-1 synchronous MOSFET. In the
default channel configuration, the PWM2 pulse terminates
1/3 of a cycle after the PWM1 pulse. The PWM3 pulse
terminates 1/3 of a cycle after PWM2.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle after
the PWM1 pulse terminates.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 6. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sampling
During the forced off-time, following a PWM transition low,
the current-sense amplifier uses the ISEN inputs to
reproduce a signal proportional to the inductor current, IL.
No matter which current-sense method is employed, the
sense current (ISEN) is simply a scaled version of the
inductor current. The sample window opens exactly 1/6 of
the switching period, tSW, after the PWM transitions low.
The sample window then stays open for a fixed amount of
time, tSAMPLE, and is equal to 1/6 of the switching period,
tSW as illustrated in Figure 3.
tSAMPLE
=
t--S----W----
6
=
--------1----------
6 ⋅ fSW
(EQ. 3)
The sampled current, at the end of the tSAMPLE, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used for
current balance, load-line regulation, and over-current
protection.
IL
PWM
ISEN
tSAMPLE
OLD SAMPLE
CURRENT
NEW SAMPLE CURRENT
SWITCHING PERIOD
TIME
FIGURE 3. SAMPLE AND HOLD TIMING
Current Sensing
The ISL6565A supports MOSFET rDS(ON) current sensing,
while the ISL6565B supports inductor DCR current sensing.
The internal circuitry, shown in Figures 4 and 5, represent
channel n of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 pin, as
described in the PWM Operation section.
MOSFET rDS(ON) SENSING (ISL6565A ONLY)
The ISL6565A senses the channel load current by sampling
the voltage across the lower MOSFET rDS(ON), as shown in
Figure 4. A ground-referenced operational amplifier, internal
to the ISL6565A, is connected to the PHASE node through a
resistor, RISEN. The voltage across RISEN is equivalent to
the voltage drop across the rDS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, IL. The ISEN current is
sampled and held as described in the Current Sampling
section. From Figure 4, the following equation for In is
derived where IL is the channel current.
In = IL r---DR----SI--S--(--OE----NN-----)
(EQ. 4)
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ISL6565.PDF ] | |
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