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PDF ISL6561 Data sheet ( Hoja de datos )
| Número de pieza | ISL6561 | |
| Descripción | Multi-Phase PWM Controller with Precision Rds(on) or DCR Differential Current Sensing for VR10.X Application | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
March 2003
ISL6561
FN9098.1
Multi-Phase PWM Controller with
Precision Rds(on) or DCR Differential
Current Sensing for VR10.X Application
The ISL6561 controls microprocessor core voltage regulation
by driving up to 4 synchronous-rectified buck channels in
parallel. Multi-phase buck converter architecture uses
interleaved timing to multiply channel ripple frequency and
reduce input and output ripple currents. Lower ripple results in
fewer components, lower component cost, reduced power
dissipation, and smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6561 features a high
bandwidth control loop and ripple frequencies of >4MHz to
provide optimal response to the transients.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6561
senses current by utilizing patented techniques to measure
the voltage across the on resistance, rDS(on), of the lower
MOSFETs or DCR of the output inductor during the lower
MOSFET conduction intervals. Current sensing provides the
needed signals for precision droop, channel-current
balancing, and over-current protection.
The accuracy of the current-sensing method is enhanced by
the ISL6561’s temperature compensation function. Droop
accuracy can be affected by increasing rDS(on) or DCR with
elevated temperature. The ISL6561 uses an internal
temperature-sensing element to provide programmable
temperature compensation. Correctly applied, temperature
compensation can completely nullify the effect of rDS(on) or
DCR temperature sensitivity.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The threshold-
sensitive enable input is available to accurately coordinate
the start up of the ISL6561 with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting. The ISL6561
uses 5V bias and has a built-in shunt regulator to allow 12V
bias using only a small external limiting resistor.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. NO.
ISL6561CR
0 to 105 40 Ld 6x6 QFN L40.6X6
Features
• Precision Multi-Phase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Reference-Voltage Offset
• Precision RDS(on) or DCR Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
- Low-Cost, Lossless Current Sensing
• Internal Shunt Regulator for 5V or 12V Biasing
• Microprocessor Voltage Identification Input
- Dynamic VID™ technology
- 6-Bit VID Input
- .8375V to 1.600V in 12.5mV Steps
• Threshold-Sensitive Enable Function for synchronizing
with driver POR
• Over Current Protection
• Over-Voltage Protection
- No Additional External Components Needed
- OVP Pin to drive opitional Crowbar Device
• 2, 3, or 4 Phase Operation
• Greater Than 1MHz Operation (> 4MHz Ripple)
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Pinout
ISL6561 (40-PIN QFN)
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
VID12.5 6
GND 7
OFS 8
TCOMP 9
DAC 10
30 ISEN4+
29 ISEN4-
28 ISEN2-
27 ISEN2+
26 PWM2
25 PWM1
24 ISEN1+
23 ISEN1-
22 ISEN3-
21 ISEN3+
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID™ is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1 page  
ISL6561
Typical Application - 4-Phase Buck Converter with DCR Sensing and External NTC
+5V
VIDPGOOD
PGOOD
OVP
VID4
VID3
VID2
FB
IDROOP
VDIFF
COMP REF
DAC
VSEN
RGND
VCC
ENLL
ISL6561
ISEN1+
ISEN1-
PWM1
PWM2
VID1
VID0
ISEN2+
ISEN2-
PWM3
VID12.5
ISEN3+
ISEN3-
OFS
FS
PWM4
ISEN4+
ISEN4-
R T TCOMP GND EN
+12V
+12V
VCC
BOOT
UGATE
PVCC
PWM
PHASE
HIP6601B
DRIVER
LGATE
GND
VIN
NTC
THERMISTOR
+12V
VCC
BOOT
PVCC
UGATE
PHASE
HIP6601B
PWM
DRIVER
LGATE
GND
VIN
+12V
VCC
PVCC
PWM
BOOT
UGATE
HIP6601B
DRIVER
PHASE
LGATE
GND
VIN
µP
LOAD
+12V
VCC
BOOT
UGATE
PVCC
PWM
PHASE
HIP6601B
DRIVER
LGATE
GND
VIN
5
5 Page 
ISL6561
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
IC, PP=
(---V----I--N-----–-----N------V-----O----U----T----)---V-----O----U-----T-
LfS VIN
(EQ. 2)
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V
load from a 12V input. The RMS input capacitor current is
5.9A. Compare this to a single-phase converter also
stepping down 12V to 1.5V at 36A. The single-phase
converter has 11.9A RMS input capacitor current. The
single-phase converter must use an input capacitor bank
with twice the RMS current capacity as the equivalent three-
phase converter.
Figures 16, 17 and 18 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 19 shows the single
phase input-capacitor RMS current for comparison.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6561
is four. One switching cycle is defined as the time between
PWM1 pulse termination signals. The pulse termination
signal is the internally generated clock signal that triggers
the falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency
set by the resistor between the FS pin and ground. Each
cycle begins when the clock signal commands the channel-1
PWM output to go low. The PWM1 transition signals the
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and turn on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/4 of a cycle after PWM1. The PWM3 output
follows another 1/4 of a cycle after PWM2. PWM4 terminates
another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments.
Once a PWM signal transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 4. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal, turns off the synchronous MOSFET
and turns on the upper MOSFET. The PWM signal remains
high until the pulse termination signal commands the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
The ISL6561 supports inductor DCR sensing or MOSFET
rDS(ON) sensing. The internal circuitry, shown in Figures 3
and 5, represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending on the status of the PWM3 and
PWM4 pins, as described in the PWM Operation section.
MOSFET rDS(ON) Sensing
The controller can sense the channel load current by
sampling the voltage across the lower MOSFET rDS(ON) as
in Figure 6. The amplifier is ground-reference by connecting
ISEN
=
IL
r---D-----S-----(---O-----N-----)
RISEN
In
SAMPLE
&
HOLD
-
+
ISEN+(n)
RISEN
(PTC)
ISEN-(n)
VIN
IL
-
IL rDS(ON)
+
N-CHANNEL
MOSFETs
ISL6561 INTERNAL CIRCUIT EXTERNAL CIRCUIT
FIGURE 3. MOSFET RDS(ON) CURRENT-SENSING CIRCUIT
the ISEN- input to the source of the lower MOSFET. ISEN+
connects to the PHASE node through a resistor RISEN. The
voltage across RISEN is equivalent to the voltage drop
across the rDS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN+ pin is
proportional to the channel current IL. The ISEN current is
then sampled and held after sufficient settling time as
described in current sampling section. The sampled current
In, is used for channel-current balance, load-line regulation,
and overcurrent protection. From Figure 4, the following
equation for ISEN is derived
ISEN
=
IL
r---D----S----(--O-----N----)
RISEN
(EQ. 3)
where IL is the channel current.
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ISL6561.PDF ] | |
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