ISL6559 Datasheet PDF - Intersil Corporation
| Part Number | ISL6559 | |
| Description | Multi-Phase PWM Controller | |
| Manufacturers | Intersil Corporation | |
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®
Data Sheet
November 2003
ISL6559
FN9084.5
Multi-Phase PWM Controller
The ISL6559 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6559 uses cost and space-saving rDS(ON) sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ± 1% over temperature.
Outstanding features of this controller IC include
Dynamic VIDTM technology allowing seamless on-the-fly VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on VIN, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. #
ISL6559CB
0 to 70 28 Ld SOIC M28.3
ISL6559CB-T
28 Ld SOIC Tape and Reel
ISL6559CR
0 to 70 32 Ld 5x5 QFN L32.5x5
ISL6559CR-T
32 Ld 5x5 QFN Tape and Reel
Features
• Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
• Active Channel Current Balancing
• Precision rDS(ON) Current Sharing
- Lossless
- Low Cost
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
- ± 1% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 4MHz)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
Pinouts
ISL6559CB (28 LEAD SOIC)
TOP VIEW
ISL6559CR (32 LEAD QFN)
TOP VIEW
GND 1
OVP 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
OFS 8
COMP 9
FB 10
IOUT 11
VDIFF 12
VSEN 13
RGND 14
28 EN
27 FS/DIS
26 PGOOD
32 31 30 29 28 27 26 25
25 PWM4 VID2 1
24 PWM4
24 ISEN4 VID1 2
23 ISEN4
23 ISEN1 VID0 3
22 ISEN1
22 PWM1
NC 4
21 PWM1
21 PWM2 OFS 5
20 PWM2
20 GND
19 ISEN2
18 ISEN3
17 PWM3
COMP 6
19 GND
FB 7
18 ISEN2
NC 8
17 ISEN3
9 10 11 12 13 14 15 16
16 VCC
15 GND
NC = NO CONNECT
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
Dynamic VID is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
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ISL6559
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC. Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
ERROR AMPLIFIER
Open-Loop Gain
Open-Loop Bandwidth
Slew Rate
Maximum Output Voltage
Source Current
RL = 10kΩ to ground
CL = 100pF, RL = 10kΩ to ground
CL = 100pF, Load = ±400mA
RL = 10kΩ to ground
- 72 -
- 18 -
- 7.1 11
3.6 4.5
-
3.0 7.0 9.0
Sink Current
1.6 3.0 5.4
REMOTE-SENSE AMPLIFIER
Input Impedance
- 80 -
Bandwidth
- 20 -
Slew Rate
-6-
SENSE CURRENT
IOUT Accuracy
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 50µA
-5 - 5
ISEN Offset Voltage
-6-
Over-Current Trip Level
72 90 108
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
Under-Voltage Offset From VID
IPGOOD = 4mA
VSEN Falling
- - 0.4
320 350 420
Over-Voltage Threshold
VSEN Rising
2.08 2.13 2.20
OVP Voltage
IOVP = 100mA, VCC = 5V
NOTE:
3. These parts are designed and adjusted for accuracy within the system tolerance
2.2 3.28 4.0
UNITS
dB
MHz
V/µs
V
mA
mA
kΩ
MHz
V/µs
%
mV
µA
V
mV
V
V
Functional Pin Description
ISL6559CB (28 LEAD SOIC)
TOP VIEW
ISL6559CR (32 LEAD QFN)
TOP VIEW
GND 1
OVP 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
OFS 8
COMP 9
FB 10
IOUT 11
VDIFF 12
VSEN 13
RGND 14
28 EN
27 FS/DIS
26 PGOOD
25 PWM4
24 ISEN4
23 ISEN1
22 PWM1
21 PWM2
32 31 30 29 28 27 26 25
VID2 1
24 PWM4
VID1 2
23 ISEN4
VID0 3
22 ISEN1
NC 4
21 PWM1
OFS 5
20 PWM2
20 GND COMP 6
19 GND
19 ISEN2
FB 7
18 ISEN2
18 ISEN3
17 PWM3
NC 8
17 ISEN3
9 10 11 12 13 14 15 16
16 VCC
15 GND
NC = NO CONNECT
GND
Bias and reference ground for the IC.
OVP
Over-voltage protection pin. This pin pulls to VCC and is
latched when an over-voltage condition is detected. Connect
this pin to the gate of an SCR or MOSFET tied across VIN
and ground to prevent damage to a load device.
VID4, VID3, VID2, VID1, VID0
The state of these five inputs program the internal DAC,
which provides the reference voltage for output regulation.
Connect these pins to either open-drain or active pull-up
type outputs. Pulling these pins above 2.9V can cause a
reference offset inaccuracy.
OFS
Connecting a resistor between this pin and ground creates a
positive offset voltage which is added to the DAC voltage,
allowing easy implementation of load-line regulation. For no
offset, simply tie this pin to ground.
FB and COMP
The internal error amplifier inverting input and output
respectively. Connect the external R-C feedback
compensation network of the regulator to these pins.
IOUT
The current carried out of this pin is proportional to output
current and can be used to incorporate output voltage droop
5
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| Information | Total 22 Pages | |
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