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73K324L の電気的特性と機能

73K324LのメーカーはETCです、この部品の機能は「CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem」です。


製品の詳細 ( Datasheet PDF )

部品番号 73K324L
部品説明 CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem
メーカ ETC
ロゴ ETC ロゴ 




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73K324L Datasheet, 73K324L PDF,ピン配置, 機能
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
DESCRIPTION
The 73K324L is a highly integrated single-chip
modem IC which provides the functions needed to
design a Quad-mode CCITT and Bell 212A
compatible modem capable of operation over dial-up
lines. The 73K324L adds V.23 capability to the
CCITT modes of TDK Semiconductor Corporation's
73K224 one-chip modem, allowing a one-chip
implementation in designs intended for European
markets which require this added Modulation mode.
The 73K324L offers excellent performance and a
high level of functional integration in a single IC. The
device supports V.22bis, V.22, Bell 212A, V.21, and
V.23 operating modes, allowing both synchronous
and asynchronous operation as defined by the
appropriate standard.
The 73K324L is designed to appear to the Systems
Engineer as a microprocessor peripheral, and will
easily interface with popular one-chip
microcontrollers (80C51 typical) for control of
modem functions through its 8-bit multiplexed
address/data bus. A serial control bus is available
for applications not requiring a parallel interface. An
optional package with only the serial control bus is
also available. Data communications occurs through
a separate serial port.
(continued)
FEATURES
April 2000
One chip Multi-mode CCITT V.22bis, V.22, V.21,
V.23 and Bell 212A compatible modem data pump
FSK (75, 300, 1200 bit/s), DPSK (600, 1200 bit/s),
or QAM (2400 bit/s) encoding
Pin and software compatible with other
TDK Semiconductor Corporation K-Series family
one-chip modems
Interfaces directly with standard
microprocessors (8048, 80C51 typical)
Serial and parallel microprocessor bus for
control
Selectable asynch/synch with internal
buffer/debuffer and scrambler/descrambler
functions
All synchronous (internal, external, slave) and
Asynchronous Operating modes
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), and selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
DTMF, answer, calling, SCT and guard tone
generators
Test modes available: ALB, DL, RDL; Mark, Space
and Alternating bit pattern generators
CMOS technology for low power consumption
(100 MW @ 5 V) with power-down mode
(15 mW @ 5V)
4-wire full duplex operation in all modes
BLOCK DIAGRAM
8 - BIT
mP
BUS
I/F
TXD
RXD
SERIAL
I/F
BUFFER
FSK
MODULATOR
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
SCRAMBLER
DIBIT/
QUADBIT
ENCODER
FIR
PULSE
SHAPER
QAM/
DPSK
MODULATOR
+
EQUALIZER
FILTER
+
ATTEN
FILTER
TXA
DEBUFFER
DE-
SCRAMBLER
DIBIT/
QUADBIT
DECODER
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
FILTER
A/D
AGC
EQUALIZER
FIXED
DEMOD
6 dB
GAIN
BOOST
FILTER
6 dB
GAIN BOOST
FILTER
RXA
TONE DETECTION

1 Page





73K324L pdf, ピン配列
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
ASYNCHRONOUS MODE
The Asynchronous mode is used for communication
with asynchronous terminals which may transfer
data at 600, 1200, or 2400 bit/s +1%, -2.5% even
though the modem’s output is limited to the nominal
bit rate ±0.01% in DPSK and QAM modes. When
transmitting in this mode the serial data on the TXD
input is passed through a rate converter which
inserts or deletes stop bits in the serial bit stream in
order to output a signal that is the nominal bit rate
±0.01%. This signal is then routed to a data
scrambler and into the analog modulator where di-bit
or quad-bit encoding results in the output signal.
Both the rate converter and scrambler can be
bypassed for handshaking and synchronous
operation as selected. Received data is processed
in a similar fashion except that the rate converter
now acts to reinsert any deleted stop bits and output
data to the terminal at no greater than the bit rate
plus 1%. An incoming break signal (low through two
characters) will be recognized and passed through
without incorrectly inserting a stop bit.
The SYNC/ASYNC converter has an extended
Overspeed mode which allows selection of an output
speed range of either +1% or +2.3%. In the
extended Overspeed mode, some stop bits are
output at 7/8 the normal width.
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM
or DPSK modes. Operation is similar to that of the
Asynchronous mode except that data must be
synchronized to a clock and no variation in data
transfer rate is allowable. Serial input data appearing
at TXD must be valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz
signal in Internal mode and is connected internally to
the RXCLK pin in Slave mode. Receive data at the
RXD pin is clocked out on the falling edge of
RXCLK. The asynch/synch converter is bypassed
when Synchronous mode is selected and data is
transmitted out at essentially the same rate as it is
input.
PARALLEL CONTROL INTERFACE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a
control microprocessor as seven consecutive
memory locations. Six control registers are
read/write. The detect and ID registers are read only
and cannot be modified except by modem response
to monitored parameters.
SERIAL CONTROL INTERFACE
The Serial Command mode allows access to the
73K324L control and status registers via a serial
control port. In this mode the A0, A1, and A2 lines
provide register addresses for data passed through
the DATA pin under control of the RD and WR lines.
A read operation is initiated when the RD line is
taken low. The next eight cycles of EXCLK will then
transfer out eight bits of the selected addresss
location LSB first. A write takes place by shifting in
eight bits of data LSB first for eight consectuive
cycles of EXCLK. WR is then pulsed low and data
transfer into the selected register occurs on the
rising edge of WR.
TONE GENERATOR
The DTMF generator controls the sending of the
sixteen standard DTMF tone pairs. The tone pair
sent is determined by selecting TRANSMIT DTMF
(bit D4) and the 4 DTMF bits (D0-D3) of the TONE
register. Transmission of DTMF tones from TXA is
gated by the TRANSMIT ENABLE bit of CR0 (bit D1)
as with all other analog signals.
FULL DUPLEX OPERATION
Four-wire full duplex operation is allowed in all
modes. This feature allows transmission and
reception in the same band for four wire applications
only.
3


3Pages


73K324L 電子部品, 半導体
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the A0, A1 and A2 address lines in Serial mode, or
the AD0, AD1 and AD2 lines in Parallel mode. The
address lines are latched by ALE. Register CR0
controls the method by which data is transferred
over the phone line. CR1 controls the interface
between the microprocessor and the 73K324L
internal state. DR is a detect register which provides
an indication of monitored modem status conditions.
TR, the tone control register, controls the DTMF
generator, answer, guard tones, SCT, calling tone,
and RXD output gate used in the modem initial
connect sequence. CR2 is the primary DSP control
interface and CR3 controls transmit attenuation and
receive gain adjustments. All registers are read/write
except for DR and ID which are read only. Register
control and status bits are identified below:
REGISTER BIT SUMMARY
REGISTER
ADDRESS
AD - A0
CONTROL
REGISTER
0
CR0
000
CONTROL
REGISTER
1
CR1
001
DETECT
REGISTER
DR
010
TONE
CONTROL
REGISTER
TR
CONTROL
REGISTER
2
CR2
CONTROL
REGISTER
3
CR3
011
100
101
DATA BIT NUMBER
D7 D6 D5 D4 D3
MODULATION
OPTION
TRANSMIT
PATTERN
1
MODULATION
TYPE
1
TRANSMIT
PATTERN
0
MODULATION
TYPE
0
ENABLE
DETECT
INTERRUPT
TRANSMIT
MODE
2
BYPASS
SCRAMBLER/
ADD PH. EQ.
(V.23)
TRANSMIT
MODE
1
CLK
CONTROL
RECEIVE
LEVEL
RXD
OUTPUT
CONTROL
PATTERN
S1 DET
TRANSMIT
GUARD TONE/
SCT/CALLING
TONE
RECEIVE
DATA
TRANSMIT
ANSWER
TONE
UNSCR.
MARK
DETECT
TRANSMIT
DTMF
CARRIER
DETECT
DTMF3
0
SPECIAL
REGISTER
CALL
INITIALIZE
TRANSMIT
S1
16 WAY
ACCESS
TXDALT
TRISTATE
TX/RXCLK
0
RECEIVE
GAIN
TRANSMIT
ATTEN.
BOOST
3
SPECIAL
REGISTER
SR
101
0
TX BAUD
RX UNSCR.
0
CLOCK
DATA
TXD
SOURCE
ID
REGISTER
ID 110
1
1
10
X
D2
TRANSMIT
MODE
0
RESET
SPECIAL
TONE
DETECT
DTMF2/
4 WIRE FDX
RESET
DSP
TRANSMIT
ATTEN.
2
SQ
SELECT 1
X
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
TEST
MODE
1
TEST
MODE
0
CALL
PROGRESS
DETECT
SIGNAL
QUALITY
DTMF1/
OVERSPEED
DTMF0/GUARD/
ANSWER/
CALLING/SCT
TRAIN
INHIBIT
TRANSMIT
ATTEN.
1
SQ
SELECT 0
EQUALIZER
ENABLE
TRANSMIT
ATTEN.
0
0
XX
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as
0's.
X = Undefined, mask in software.
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
73K324L

CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem

ETC
ETC
73K324L-28IH

CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem

ETC
ETC
73K324L-IGT

CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem

ETC
ETC
73K324L-IP

CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem

ETC
ETC


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