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6N137 の電気的特性と機能

6N137のメーカーはETCです、この部品の機能は「HIGH CMR/ VERY HIGH SPEED OPTICALLY COUPLED ISOLATOR LOGIC GATE OUTPUT」です。


製品の詳細 ( Datasheet PDF )

部品番号 6N137
部品説明 HIGH CMR/ VERY HIGH SPEED OPTICALLY COUPLED ISOLATOR LOGIC GATE OUTPUT
メーカ ETC
ロゴ ETC ロゴ 




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6N137 Datasheet, 6N137 PDF,ピン配置, 機能
6N137
ICPL2601
HIGH CMR, VERY HIGH SPEED
OPTICALLY COUPLED ISOLATOR
LOGIC GATE OUTPUT
APPROVALS
l UL recognised, File No. E91231
DESCRIPTION
The 6N137 / ICPL2601 optocouplers consist of
a GaAsP light emitting diode and a high gain
integrated photo detector to provide 2500Volts
RMS
electrical isolation between input and output. An
enable input allows the detector to be strobed.
The output of the detector I.C. is an open
collector Schottky clamped transistor. The
ICPL2601 has an internal shield which provides
a guaranteed common mode transient immunity
specification of 1000V/µs minimum.This unique
design provides maximum ac and dc circuit
isolation while achieving TTL compatibility. The
coupled parameters are guaranteed over the
temperature range of 0°C to 70°C, such that a
maximum input signal of 5mA will provide a
minimum output sink current of 13mA(equivalent
to fan-out of eight gates)
FEATURES
l High speed - 10MBit/s
l High Common Mode Transient
Immunity 10kV/µs typical
l Logic gate output
l ICPL2601 has improved noise shield
for superior common mode rejection
l Options :-
10mm lead spread - add G after part no.
Surface mount - add SM after part no.
Tape&reel - add SMT&R after part no.
APPLICATIONS
l Line receiver, data transmission
l Computer-peripheral interface
l Data multiplexing
l Pulse transformer replacement
OPTION SM
SURFACE MOUNT
OPTION G
7.62
1.2 1.4
0.6 0.9
10.2
9.5
0.3
10.16
Dimensions in mm
2.54 VCC
18
6.9 2
6.3 3
7
6
1.3
9.7
9.1
4*
5
GND
* ICPL2601 NOISE SHIELD
7.62
4.0
3.6
0.5
3.3
0.5 1.3
TRUTH TABLE
0.3
15°
Max
INPUT
H
L
H
L
ENABLE
H
H
L
L
OUTPUT A 0.1µF bypass
L capacitor must be
H connected between
H
pins 8 and 5 ( See
note 1)
H
ABSOLUTE MAXIMUM RATINGS
(25°C unless otherwise specified)
Storage Temperature
-55°C to + 125°C
Operating Temperature
0°C to + 70°C
Lead Soldering Temperature
(1/16 inch (1.6mm) from case for 10 secs) 260°C
INPUT DIODE
Average Forward Current
Reverse Voltage
20mA
5V
DETECTOR
Enable Input Voltage ( VE )
(not to exceed VCC by more than 500mV)
Reverse Supply Voltage(-V )
CC
Supply Voltage(V )
CC
(1 minute maximum)
Output Current ( IO )
Output Voltage ( VO )
Collector Output Power Dissipation
5.5V
-500mV
7V
25mA
7V
40mW
ISOCOMCOMPONENTSLTD
Unit 25B, Park View Road West,
Park View Industrial Estate, Brenda Road
Hartlepool, TS25 1YD England Tel: (01429)863609
Fax : (01429) 863581 e-mail [email protected]
http://www.isocom.com
19/4/99
ISOCOM INC
1024 S. Greenville Ave, Suite 240,
Allen, TX 75002 USA
Tel:(214)495-0755 Fax:(214)495-0901
http://www.isocom.com
DB91063-AAS/A1

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6N137 pdf, ピン配列
SWITCHING SPECIFICATIONS AT TA = 25°C ( VCC = 5V, IF = 7.5mA Unless otherwise noted )
PARAMETER
Propagation Delay Time
to Logic Low at Output
( fig 1 )( note4 )
SYM DEVICE MIN TYP MAX UNITS TEST CONDITION
t
PHL
55 75 ns
R
L
=
350Ω,
C
L
=
15pF
Propagation Delay Time
to Logic High at Output
( fig 1 )( note5 )
tPLH
45 75 ns
RL = 350Ω, CL = 15pF
Propagation Delay Time
of Enable from VEH to VEL
( note6 )
tEHL
14 ns RL = 350Ω, CL = 15pF
VEL = 0V, VEH = 3V
Propagation Delay Time
of Enable from V to V
EL EH
( note7 )
t
ELH
25
ns
R
L
=
350Ω,
C
L
=
15pF
VEL = 0V, VEH = 3V
Common Mode Transient
Immunity at Logic High
Level Output ( fig 2 )( note8 )
CM 6N137
10000
H
ICPL2601 1000 10000
V/µs
V/µs
I = 0mA, V = 50V
F CM PP
RL= 350Ω,VOH= 2Vmin.
Common Mode Transient
Immunity at Logic Low
Level Output ( fig 2 )( note9 )
CM 6N137
-10000
L
ICPL2601 -1000 -10000
V/µs
V/µs
V = 50V
CM PP
RL=350Ω,VOL=0.8Vmax.
NOTES:-
1 Bypassing of the power supply line is required, with a 0.01µF ceramic disc capacitor adjacent to
each isolator. The power supply bus for the isolator(s) should be seperate from the bus for any
active loads. Otherwise a larger value of bypass capacitor (up to 0.1µF) may be needed to supress
regenerative feedback via the power supply.
2 Peaking circuits may produce transient input currents up to 50mA, 50ns maximum pulse width,
provided average current does not exceed 20mA.
3 Device considered a two terminal device; pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7
and 8 shorted together.
4 The tPHL propagation delay is measured from the 3.75 mA level Low to High transition of the input
current pulse to the 1.5V level on the High to Low transition of the output voltage pulse.
5 The tPLH propagation delay is measured from the 3.75mA level High to Low transition of the input
current pulse to the 1.5V level on the Low to High transition of the output voltage pulse.
6 The tEHL enable input propagation delay is measured from the 1.5V level on the Low to High transition of
the enable input voltage pulse to the 1.5V level on the High to Low of the output voltage pulse.
7 The tELH enable input propagation delay is measured from the 1.5V level on the High to Low transition of
the enable input voltage pulse to the 1.5V level on the Low to High of the output voltage pulse.
8 CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output
will remain in a high logic state (ie Vout > 2.0V).
9 CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output
will remain in a low logic state (ie Vout < 0.8V)
10 No external pull up is required for a high logic state on the enable input.
IF
0
V
O
t
PHL
FIG.1 SWITCHING TEST CIRCUIT
1.5V
t
PLH
5V
1.5V
VOL
PULSE
GENERATOR
Z
O
=
50
tr = 5ns
10% Duty Cycle
1/f < 100µs
I
F
I Monitor
F
100
1
2
3
4
8 5V
7 RL
6 VO
5
CL = 15pF
19/4/99
DB91063-AAS/A1


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