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PDF 6809 Data sheet ( Hoja de datos )
| Número de pieza | 6809 | |
| Descripción | DABiC-IV/ 10-BIT SERIAL-INPUT/ LATCHED SOURCE DRIVERS | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 6809 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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6809 AND
6810
A6810xA
OUT8 1
OUT7 2
OUT6 3
CLOCK 4 CLK
GROUND 5
LOGIC
SUPPLY
6 VDD
STROBE 7 ST
OUT 5 8
OUT4 9
18 OUT 9
LATCHES
REGISTER
REGISTER
LATCHES
17 OUT 10
16
SERIAL
DATA OUT
VBB 15
LOAD
SUPPLY
14 SERIAL
DATA IN
BLNK 13 BLANKING
12 OUT1
11 OUT 2
10 OUT 3
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
The A6809– and A6810– devices combine 10-bit CMOS shift
registers, accompanying data latches and control circuitry with bipolar
sourcing outputs and pnp active pull downs. Designed primarily to
drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings
also allow these devices to be used in many other peripheral power
driver applications. The A6809– and A6810– feature an increased data
input rate (compared with the older UCN/UCQ5810-F) and a con-
trolled output slew rate. The A6809xLW and A6810xLW are identical
except for pinout.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are avail-able as
the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits).
The A6809– and A6810– output source drivers are npn Darling-
tons, capable of sourcing up to 40 mA. The controlled output slew rate
reduces electromagnetic noise, which is an important consideration in
systems that include telecommunications and/or microprocessors and
to meet government emissions regulations. For inter-digit blanking, all
output drivers can be disabled and all sink drivers turned on with a
BLANKING input high. The pnp active pull-downs will sink at least
2.5 mA.
All devices are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applica-
tions. The A6810– is provided in three package styles for through-hole
DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area
surface-mount PLCC (suffix -EP). The A6809– is provided in the
SOIC (suffix -LW) only. Copper lead frames, low logic-power dissi-
pation, and low output-saturation voltages allow all devices to source
25 mA from all outputs continuously over the maximum operating
temperature range.
FEATURES
I Controlled Output Slew Rate I Low Output-Saturation Voltages
I High-Speed Data Storage I Low-Power CMOS Logic
I 60 V Minimum
and Latches
Output Breakdown
I Improved Replacements
I High Data Input Rate
for TL4810–, UCN5810–,
I PNP Active Pull-Downs
and UCQ5810–
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6810SLW .
1 page  
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT
AB
DATA
50%
t p(CH-SQX)
50%
DE
DATA
STROBE
50%
BLANKING
OUT N
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
10%
Dwg. WP-029
BLANKING
OUT N
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t en(BQ)
t dis(BQ)
tr
DATA
10%
tf
90%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Dwg. WP-030
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
www.allegromicro.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 6809.PDF ] | |
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