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74AC00 の電気的特性と機能

74AC00のメーカーはFairchild Semiconductorです、この部品の機能は「Quad 2-Input NAND Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74AC00
部品説明 Quad 2-Input NAND Gate
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74AC00 Datasheet, 74AC00 PDF,ピン配置, 機能
January 2008
74AC00, 74ACT00
Quad 2-Input NAND Gate
Features
ICC reduced by 50%
Outputs source/sink 24mA
ACT00 has TTL-compatible inputs
General Description
The AC00/ACT00 contains four, 2-input NAND gates.
Ordering Information
Order
Number
Package
Number
Package Description
74AC00SC
74AC00SJ
74AC00MTC
74AC00PC
74ACT00SC
74ACT00SJ
74ACT00MTC
74ACT00PC
M14A
M14D
MTC14
N14A
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
An, Bn
On
Description
Inputs
Outputs
©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1
www.fairchildsemi.com

1 Page





74AC00 pdf, ピン配列
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VOL Maximum LOW Level
Output Voltage
IIN(3)
IOLD
IOHD
ICC(3)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current(2)
Maximum Quiescent
Supply Current
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
Conditions
VOUT = 0.1V
or VCC – 0.1V
VOUT = 0.1V
or VCC – 0.1V
IOUT = –50µA
VIN = VIL or VIH,
IOH = –12mA
VIN = VIL or VIH,
IOH = –24mA
VIN = VIL or VIH,
IOH = –24mA(1)
IOUT = 50µA
VIN = VIL or VIH,
IOL = 12mA
VIN = VIL or VIH,
IOL = 24mA
VIN = VIL or VIH,
IOL = 24mA(1)
VI = VCC, GND
TA = +25°C TA = –40°C to +85°C
Typ.
Guaranteed Limits
1.5 2.1
2.1
2.25 3.15
3.15
2.75 3.85
3.85
1.5 0.9
0.9
2.25 1.35
1.35
2.75 1.65
1.65
2.99 2.9
2.9
4.49 4.4
4.4
5.49 5.4
5.4
2.56 2.46
Units
V
V
V
3.86 3.76
4.86 4.76
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.1
0.1
0.1
0.44
V
0.36 0.44
0.36 0.44
±0.1 ±1.0
µA
5.5 VOLD = 1.65V Max.
5.5 VOHD = 3.85V Min.
5.5 VIN = VCC or GND
2.0
75
–75
20.0
mA
mA
µA
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1
3
www.fairchildsemi.com


3Pages


74AC00 電子部品, 半導体
Physical Dimensions
8.75
8.50
7.62
14
6.00
A
8
B
4.00
3.80
0.65
5.60
PIN ONE
INDICATOR
1
1.27
(0.33)
7
0.51
0.35
1.70 1.27
LAND PATTERN RECOMMENDATION
0.25 M C B A
1.75 MAX
1.50
1.25
R0.10
R0.10
8°
0°
SEE DETAIL A
0.25
0.10 C
0.10 C
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
X 45°
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE FLASH OR BURRS.
D) LANDPATTERN STANDARD:
0.36
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1
6
www.fairchildsemi.com

6 Page



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共有リンク

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