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74ABT20DのメーカーはNXP Semiconductorsです、この部品の機能は「Dual 4-input NAND gate」です。 |
部品番号 | 74ABT20D |
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部品説明 | Dual 4-input NAND gate | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューと74ABT20Dダウンロード(pdfファイル)リンクがあります。 Total 3 pages
Philips Semiconductors
Dual 4-input NAND gate
Product specification
74ABT20
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
Tamb = 25°C;
GND = 0V
tPLH
tPHL
tOSLH
tOSHL
CIN
Propagation
delay
An, Bn, Cn, Dn
to Yn
Output to
Output skew
Input
capacitance
CL = 50pF;
VCC = 5V
VI = 0V or VCC
ICC
Total supply
current
Outputs disabled;
VCC = 5.5V
TYPICAL UNIT
2.7
2.2
ns
0.3 ns
3 pF
50 µA
PIN CONFIGURATION
A0 1
B0 2
NC 3
C0 4
D0 5
Y0 6
GND 7
14 VCC
13 D1
12 C1
11 NC
10 B1
9 A1
8 Y1
SA00350
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1, 2, 4, 5, 9,
10, 12, 13
An, Bn,
Cn, Dn
Data inputs
6, 8 Yn Data outputs
7 GND Ground (0V)
14 VCC Positive supply voltage
LOGIC SYMBOL
1 2 4 5 9 10 12 13
A0 B0 C0 D0 A1 B1 C1 D1
VCC = Pin 14
GND = Pin 7
Y0 Y1
68
SA00351
LOGIC DIAGRAM
A0
B0
C0
D0
1
2
4
5
VCC = Pin 14
GND = Pin 7
9
A1
10
B1
12
C1
13
D1
6
Y0
8
Y1
LOGIC SYMBOL (IEEE/IEC)
1&
2
4
5
6
SA00352
9
10
12
13
FUNCTION TABLE
INPUTS
An Bn Cn
LXX
XLX
XXL
XXX
HH
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
H
8
SF00068
OUTPUT
Dn Yn
XH
XH
XH
LH
HL
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIP
14-Pin plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT20 N
74ABT20 D
74ABT20 DB
74ABT20 PW
NORTH AMERICA
74ABT20 N
74ABT20 D
74ABT20 DB
74ABT20PW DH
DWG NUMBER
SOT27-1
SOT108-1
SOT337-1
SOT402-1
1995 Sep 22
1 853-1811 15793
1 Page Philips Semiconductors
Dual 4-input NAND gate
Product specification
74ABT20
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25°C
VCC = +5.0V
MIN TYP MAX
Tamb = –40°C to +85°C
VCC = +5.0V ±0.5V
MIN MAX
UNIT
tPLH Propagation delay
tPHL An, Bn, Cn, Dn to Yn
1
1.0 2.7 3.9
1.0 2.2 3.4
1.0
1.0
4.6
3.8
ns
tOSHL
tOSLH1
Output to Output skew
An or Bn to Yn
2
0.3 0.5
0.5 ns
NOTE:
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same
device. The specification applies to any outputs switching in the the same direction, either HIGH–to-LOW (tOSHL) or LOW-to-HIGH (tOSLH);
parameter guaranteed by design.
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
An, Bn,
Cn, Dn
VM VM
tPHL
tPLH
Yn VM VM
SA00353
Waveform 1. Propagation Delay for Inverting Outputs
TEST CIRCUIT AND WAVEFORMS
VCC
PULSE
GENERATOR
VIN
RT
D.U.T.
VOUT
CL
RL
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT
OUTPUT
OUTPUT N
same part
tPLH
MIN
tPHL
MIN
tPLH MAX
tOSLH
tPHLMAX
tOSHL
Waveform 2. Common edge skew
SA00381
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
VM
10%
tW
VM
10%
tTHL (tF)
tTLH (tR)
90%
VM
90%
VM
tW
VM = 1.5V
Input Pulse Definition
90%
AMP (V)
0V
tTLH (tR)
tTHL (tF)
AMP (V)
10%
0V
FAMILY
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate tW
tR
tF
74ABT
3.0V
1MHz 500ns 2.5ns 2.5ns
SH00067
1995 Sep 22
3
3Pages | |||
ページ | 合計 : 3 ページ | ||
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PDF ダウンロード | [ 74ABT20D データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
74ABT20 | Dual 4-input NAND gate | NXP Semiconductors |
74ABT20D | Dual 4-input NAND gate | NXP Semiconductors |
74ABT20DB | Dual 4-input NAND gate | NXP Semiconductors |
74ABT20N | Dual 4-input NAND gate | NXP Semiconductors |