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74ABT16821A の電気的特性と機能

74ABT16821AのメーカーはNXP Semiconductorsです、この部品の機能は「20-bit bus-interface D-type flip-flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 74ABT16821A
部品説明 20-bit bus-interface D-type flip-flop
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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74ABT16821A Datasheet, 74ABT16821A PDF,ピン配置, 機能
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger;
3-state
Rev. 03 — 16 March 2010
Product data sheet
1. General description
The 74ABT16821A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT16821A has two 10-bit, edge-triggered registers, with each register coupled to
a 3-state output buffer. The two sections of each register are controlled independently by
the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active-LOW output enable (nOE) controls all ten 3-state buffers independent of the
register operation. When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features and benefits
„ 20-bit positive-edge triggered register
„ Multiple VCC and GND pins minimize switching noise
„ Live insertion and extraction permitted
„ Output capability: +64 mA and 32 mA
„ Power-up 3-state
„ Power-up reset
„ Latch-up protection exceeds 500 mA per JESD78B class II level A
„ ESD protection:
‹ HBM JESD22-A114F exceeds 2000 V
‹ MM JESD22-A115-A exceeds 200 V

1 Page





74ABT16821A pdf, ピン配列
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
55 54 52 51 49 48 47 45 44 43
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
56 1CP
1 1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2 3 5 6 8 9 10 12 13 14
Fig 2. Logic symbol
42 41 40 38 37 36 34 33 31 30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29 2CP
28 2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15 16 17 19 20 21 23 24 26 27
001aae856
nD0
D
nD1
D
nD2
D
nD3
D
nD4
D
nD5
D
nD6
D
nD7
D
nD8
D
nD9
D
nCP
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nOE
nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9
001aae857
Fig 3. Logic diagram
74ABT16821A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 March 2010
© NXP B.V. 2010. All rights reserved.
3 of 16


3Pages


74ABT16821A 電子部品, 半導体
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VCC supply voltage
VI input voltage
VO output voltage
output in OFF-state or HIGH-state
IIK
input clamping current
VI < 0 V
IOK
output clamping current
VO < 0 V
IO output current
output in LOW-state
output in HIGH-state
Tj junction temperature
Tstg storage temperature
Min
0.5
[1] 1.2
[1] 0.5
18
50
-
64
[2] -
65
Max
+7.0
+7.0
+5.5
-
-
128
-
150
+150
Unit
V
V
V
mA
mA
mA
mA
°C
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC
VI
VIH
VIL
IOH
IOL
Δt/ΔV
supply voltage
input voltage
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
Tamb
ambient temperature
Conditions
in free air
Min Typ Max Unit
4.5 -
5.5 V
0-
2.0 -
VCC
V
-V
- - 0.8 V
32 - - mA
- - 64 mA
0-
10 ns/V
40 -
+85 °C
74ABT16821A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 March 2010
© NXP B.V. 2010. All rights reserved.
6 of 16

6 Page



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部品番号部品説明メーカ
74ABT16821A

20-bit bus-interface D-type flip-flop

NXP Semiconductors
NXP Semiconductors
74ABT16821A

20-bit bus-interface D-type flip-flop

Philips
Philips


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