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Número de pieza | 74ABT16543 | |
Descripción | 16-Bit Registered Transceiver with 3-STATE Outputs | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74ABT16543 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! October 1993
Revised January 1999
74ABT16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16543 16-bit transceiver contains two sets of D-
type latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. Each byte has separate control inputs, which can be
shorted together for full 16-bit operation.
Features
s Back-to-back registers for storage
s Bidirectional data path
s A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
s Separate control logic for each byte
s 16-bit version of the ABT543
s Separate controls for data flow in each direction
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16543CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16543CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011646.prf
www.fairchildsemi.com
1 page AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. VM = 1.5V
Input Pulse Requirements
Amplitude Rep. Rate
tW
tr
tf
3V
1 MHz
500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet 74ABT16543.PDF ] |
Número de pieza | Descripción | Fabricantes |
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74ABT16543 | 16-Bit Registered Transceiver with 3-STATE Outputs | Fairchild Semiconductor |
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