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74ABT16543のメーカーはNXP Semiconductorsです、この部品の機能は「16-bit latched transceivers with dual enable 3-State」です。 |
部品番号 | 74ABT16543 |
| |
部品説明 | 16-bit latched transceivers with dual enable 3-State | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューと74ABT16543ダウンロード(pdfファイル)リンクがあります。 Total 12 pages
INTEGRATED CIRCUITS
74ABT16543
74ABTH16543
16-bit latched transceivers with
dual enable (3-State)
Product specification
Supersedes data of 1995 Aug 17
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors
1 Page Philips Semiconductors
16-bit latched transceivers with dual enable
(3-State)
Product specification
74ABT16543
74ABTH16543
LOGIC SYMBOL (IEEE/IEC)
1OEBA
1EBA
1LEBA
1OEAB
1EAB
1LEAB
2OEBA
2EBA
2LEBA
2OEAB
2EAB
2LEAB
56
54
55
1
3
2
29
31
30
28
26
27
1A0 5
1A1 6
1A2 8
1A3 9
1A4 10
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
2A3 19
2A4 20
2A5 21
2A6 23
2A7 24
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
∇3
6D
5D
4∇
∇9 11D
12D 10 ∇
52 1B0
51 1B1
49 1B2
48 1B3
47 1B4
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
38 2B3
37 2B4
36 2B5
34 2B6
33 2B7
SH00036
PIN CONFIGURATION
1OEAB 1
1LEAB 2
1EAB 3
GND 4
1A0 5
1A1 6
VCC
1A2
1A3
7
8
9
1A4 10
GND 11
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
GND 18
2A3 19
2A4 20
2A5 21
VCC 22
2A6 23
2A7 24
GND 25
2EAB 26
2LEAB 27
2OEAB 28
56 1OEBA
55 1LEBA
54 1EBA
53 GND
52 1B0
51 1B1
50 VCC
49 1B2
48 1B3
47 1B4
46 GND
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
39 GND
38 2B3
37 2B4
36 2B5
35 VCC
34 2B6
33 2B7
32 GND
31 2EBA
30 2LEBA
29 2OEBA
SH00037
1998 Feb 27
3
3Pages Philips Semiconductors
16-bit latched transceivers with dual enable
(3-State)
Product specification
74ABT16543
74ABTH16543
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VIH
VIL
IOH
IOL
∆t/∆v
Tamb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
LIMITS
Min Max
4.5 5.5
0 VCC
2.0
0.8
–32
64
0 10
–40 +85
UNIT
V
V
V
V
mA
mA
ns/V
°C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
MIN TYP MAX
Tamb = –40°C
to +85°C
MIN MAX
UNIT
VIK
VOH
VOL
VRST
Input clamp voltage
High-level output voltage
Low-level output voltage
Power-up output voltage3
VCC = 4.5V; IIK = –18mA
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; IO = 1mA; VI = GND or VCC
–1.2 –1.2
2.5 2.9
2.5
3.0 3.4
3.0
2.0 2.4
2.0
0.36 0.55
0.55
0.13 0.55
0.55
V
V
V
V
V
V
II
Input leakage
current
VCC = 5.5V; VI = GND or 5.5V
Control
pins
"0.01 ±1.0
±1.0 µA
IHOLD
Bus Hold current A or B
Ports5 74ABTH16543
VCC = 4.5V; VI = 0.8V
VCC = 4.5V; VI = 2.0V
VCC = 5.5V; VI = 0 to 5.5V
35
–75
±800
35
–75 µA
IOFF Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V
"2.0 ±100
±100 µA
IPU/PD
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.0V or VCC;
VI = GND or VCC; VOE = Don’t care
"1.0 ±50
±50 µA
IIH + IOZH 3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or VIH
1.0 10
10 µA
IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or VIH
–1.0 –10
–10 µA
ICEX
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC
1.0 50
50 µA
IO Output current1
VCC = 5.5V; VO = 2.5V
–50 –100 –200 –50 –200 mA
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
0.55 2
2 mA
ICCL
ICCZ
Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
9 19
0.55 2
19 mA
2 mA
∆ICC
Additional supply current
per input pin2
74ABT16543
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
5.0 50
50 µA
∆ICC
Additional supply current
per input pin2
74ABTH16543
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
200 500
500 µA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
6
6 Page | |||
ページ | 合計 : 12 ページ | ||
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PDF ダウンロード | [ 74ABT16543 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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