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74ABT16500 の電気的特性と機能

74ABT16500のメーカーはFairchild Semiconductorです、この部品の機能は「18-Bit Universal Bus Transceivers with 3-STATE Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 74ABT16500
部品説明 18-Bit Universal Bus Transceivers with 3-STATE Outputs
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74ABT16500 Datasheet, 74ABT16500 PDF,ピン配置, 機能
April 1993
Revised January 1999
74ABT16500
18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16500 18-bit universal bus transceiver combines
D-type latches and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. Output-enable OEAB is active-high.
When OEAB is HIGH, the outputs are active. When OEAB
is LOW, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
s Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
s Flow-through architecture optimizes PCB layout
s Guaranteed latch-up protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16500CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16500CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Connection Diagram
Function Table (Note 1)
Pin Assignment for SSOP
Inputs
Output
OEAB LEAB CLKAB A
B
LXXX
Z
HHX L
L
HHXH
H
HL L
L
HL H
H
H L H X B0 (Note 2)
H L L X B0 (Note 3)
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions
were established.
Note 3: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
© 1999 Fairchild Semiconductor Corporation DS011581.prf
www.fairchildsemi.com

1 Page





74ABT16500 pdf, ピン配列
Absolute Maximum Ratings(Note 4)
Storage Temperature
65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
VCC Pin Potential to
Ground Pin
0.5V to +7.0V
Input Voltage (Note 5)
0.5V to +7.0V
Input Current (Note 5)
30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-off State
0.5V to 5.5V
in the HIGH State
Current Applied to Output
0.5V to VCC
in LOW State (Max)
twice the rated IOL (mA)
DC Latchup Source Current
Over Voltage Latchup (I/O)
500 mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
40°C to +85°C
Supply Voltage
+4.5V to +5.5V
Minimum Input Edge Rate (V/t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 4: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
IIL
VID
IIH +
IOZH
IIL +
IOZL
IOS
ICEX
IZZ
ICCH
ICCL
ICCZ
ICCT
ICCD
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional ICC/Input
Dynamic ICC
(Note 6)
No Load
Note 6: Guaranteed, but not tested.
Min
Typ
Max
Units
VCC
Conditions
2.0 V Recognized HIGH Signal
0.8 V
Recognized LOW Signal
2.5
2.0
4.75
1.2 V Min IIN = −18 mA
V Min IOH = −3 mA
V Min IOH = −32 mA
0.55 V Min IOL = 64 mA
1 µA Max VIN = 2.7V (Note 6)
1 VIN = VCC
7 µA Max VIN = 7.0V
1 µA Max VIN = 0.5V (Note 6)
1 VIN = 0.0V
V 0.0 IID = 1.9 µA
All Other Pins Grounded
10 µA 0 5.5V VOUT = 2.7V; OE, OE = 2.0V
100
10
275
50
100
1.0
68
1.0
2.5
0.23
µA 0 5.5V VOUT = 0.5V; OE, OE = 2.0V
mA
µA
µA
mA
µA
mA
mA
mA/
MHz
Max VOUT = 0V
Max VOUT = VCC
0.0 VOUT = 5.5V; All Others GND
Max All Outputs HIGH
Max An or Bn Outputs Low
Max OEn = VCC,
All Others at VCC or GND
Max VI = VCC 2.1V
All Others at VCC or GND
Max Outputs Open
Transparent Mode
One Bit Toggling, 50% Duty Cycle
3 www.fairchildsemi.com


3Pages


74ABT16500 電子部品, 半導体
Skew
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
18 Outputs Switching
CL = 250 pF
18 Outputs Switching
Units
(Note 14)
(Note 15)
Max
Max
tOSHL
(Note 16)
Pin to Pin Skew
HL Transitions
2.0 2.8
ns
tOSLH
(Note 16)
Pin to Pin Skew
LH Transitions
2.0 2.5
ns
tPS
(Note 17)
Duty Cycle
LH–HL Skew
2.0 2.8
ns
tOST
(Note 16)
Pin to Pin Skew
LH/HL Transitions
2.5 3.0
ns
tPV
(Note 18)
Device to Device Skew
LH/HL Transitions
3.0 3.5
ns
Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 15: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 16: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST). The specification is guaranteed but not tested.
Note 17: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 18: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Symbol
Parameter
Typ
CIN
Input Capacitance
5.0
CI/O (Note 19)
Output Capacitance
11.0
Note 19: CI/O is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012.
Units
pF
pF
Conditions
TA = 25°C
VCC = 0.0V
VCC = 5.0V
www.fairchildsemi.com
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共有リンク

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74ABT16500

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