DataSheet.jp

74F113SC PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 74F113SC
部品説明 Dual JK Negative Edge-Triggered Flip-Flop
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 

Total 6 pages
		

No Preview Available !

74F113SC Datasheet, 74F113SC PDF,ピン配置, 機能
April 1988
Revised July 1999
74F113
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip-
flop will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock
pulse.
Asynchronous input:
LOW input to SD sets Q to HIGH level
Set is independent of clock
Ordering Code:
Order Number Package Number
Package Description
74F113SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F113SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F113PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009473
www.fairchildsemi.com

1 Page





ページ 合計 : 6 ページ
PDF
ダウンロード
[ 74F113SC.PDF ]

共有リンク

Link :

おすすめデータシート

部品番号部品説明メーカ
74F113SC

Dual JK Negative Edge-Triggered Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor
74F113SJ

Dual JK Negative Edge-Triggered Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor

www.DataSheet.jp    |   2019   |  メール    |   最新    |   Sitemap