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74ACTQ563PC の電気的特性と機能

74ACTQ563PCのメーカーはFairchild Semiconductorです、この部品の機能は「Quiet Series Octal Latch with 3-STATE Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 74ACTQ563PC
部品説明 Quiet Series Octal Latch with 3-STATE Outputs
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74ACTQ563PC Datasheet, 74ACTQ563PC PDF,ピン配置, 機能
January 1990
Revised December 1998
74ACTQ563
Quiet SeriesOctal Latch with 3-STATE Outputs
General Description
The ACTQ563 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The ACTQ563 is functionally identical
to the ACTQ573, but with inverted outputs. The ACTQ563
utilizes Fairchild FACT Quiet Seriestechnology to guar-
antee quiet output switching and improved dynamic thresh-
old performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Outputs source/sink 24 mA
s Faster prop delays than standard ACT563
s Functionally identical to the ACTQ573 but with inverted
outputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ563PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010631.prf
www.fairchildsemi.com

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74ACTQ563PC pdf, ピン配列
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latchup Source
or Sink Current
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
± 50 mA
± 50 mA
65°C to +150°C
± 300 mA
Junction Temperature (TJ)
PDIP
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate V/t
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC TA = +25°C TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
4.5 1.5
2.0
2.0
5.5 1.5
2.0
2.0
4.5 1.5
0.8
0.8
5.5 1.5
0.8
0.8
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5
5.5
4.5 0.001
5.5 0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
IIN Maximum Input Leakage Current
IOZ Maximum 3-STATE
Leakage Current
5.5
5.5
± 0.1
± 0.25
± 1.0
± 2.5
ICCT
IOLD
IOHD
ICC
VOLP
VOLV
VIHD
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent Supply Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.0
5.0
5.0
0.6
1.1
0.6
1.9
4.0
1.5
1.2
2.2
1.5
75
75
40.0
VILD
Maximum LOW Level
Dynamic Input Voltage
5.0 1.2
0.8
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = − 50 µA
VIN = VIL or VIH
V IOH = 24 mA
IOH = 24 mA (Note 2)
IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
V Figure 1, Figure 2
(Note 4)(Note 5)
V Figure 1, Figure 2
(Note 4)(Note 5)
V (Note 4)(Note 6)
V (Note 4)(Note 6)
3 www.fairchildsemi.com


3Pages


74ACTQ563PC 電子部品, 半導体
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
VOLP/VOLV and VOHP/VOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
• Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
• Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VOHV and VOLP are measured with respect to ground reference.
Input pulses have the following characteristics:
f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with a n oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
www.fairchildsemi.com
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部品番号部品説明メーカ
74ACTQ563PC

Quiet Series Octal Latch with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor


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