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PDF HY57V641620HGLT-HI Data sheet ( Hoja de datos )
| Número de pieza | HY57V641620HGLT-HI | |
| Descripción | 4 Banks x 1M x 16Bit Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY57V641620HG-I Series
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require
low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply Note)
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
• All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by UDQM or LDQM
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V641620HGT-5I/55I/6I/7I
HY57V641620HGT-KI
HY57V641620HGT-HI
HY57V641620HGT-8I
HY57V641620HGT-PI
HY57V641620HGT-SI
HY57V641620HGLT-5I/55I/6I/7I
HY57V641620HGLT-KI
HY57V641620HGLT-HI
HY57V641620HGLT-8I
HY57V641620HGLT-PI
HY57V641620HGLT-SI
Clock Frequency
200/183/166/143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
200/183/166/143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Normal
Low power
Organization
4Banks x 1Mbits
x16
Interface
LVTTL
Package
400mil 54pin TSOP II
Note : VDD(Min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.0/Jan. 02
1
1 page  
CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Input capacitance
Data input / output capacitance
Pin
CLK
A0 ~ A11, BA0, BA1, CKE, CS, RAS,
CAS, WE, UDQM, LDQM
DQ0 ~ DQ15
OUTPUT LOAD CIRCUIT
Symbol
CI1
CI2
CI/O
Min
2
2.5
2
HY57V641620HG
Max Unit
4 pF
5 pF
6.5 pF
Output
Vtt=1.4V
RT=250 Ω
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA= -40 to 85°C, VDD=3.3±0.3VNote3)
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Symbol
ILI
ILO
VOH
VOL
Min.
-1
-1
2.4
-
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
IOH = -4mA
IOL = +4mA
Rev. 1.0/Jan. 02
5
5 Page 
COMMAND TRUTH TABLE
HY57V641620HG
Command
CKEn-1 CKEn CS
Mode Register Set
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
DQM
Auto Refresh
Burst-READ-Single-
WRITE
Entry
Self Refresh1
Exit
H
H
H
H
H
H
H
H
H
H
H
L
Precharge
power down
Entry
Exit
H
L
Clock
Suspend
Entry
Exit
H
L
XL
H
X
L
XL
XL
XL
XL
XL
HL
XL
LL
H
H
L
H
L
L
H
H
L
H
L
L
H
RAS CAS
LL
XX
HH
LH
HL
HL
LH
HH
X
LL
LL
LL
XX
HH
XX
HH
XX
HH
XX
VV
X
WE
DQM ADDR
A10/
AP
BA
LX
X
X
H
OP code
X
HX
RA
V
L
H X CA
H
V
L
L X CA
H
V
HX
LX X
LV
LX
X
VX
HX
X
L
X
A9 Pin High
(Other Pins OP code)
HX
X
X
H
X
X
H
X
X
H
X
X
X
X
V
X
X
Note
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 1.0/Jan. 02
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HY57V641620HGLT-HI.PDF ] | |
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