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5270 の電気的特性と機能

5270のメーカーはAeroflex Circuit Technologyです、この部品の機能は「ACT5270 64-Bit Superscaler Microprocessor」です。


製品の詳細 ( Datasheet PDF )

部品番号 5270
部品説明 ACT5270 64-Bit Superscaler Microprocessor
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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5270 Datasheet, 5270 PDF,ピン配置, 機能
ACT5270
64-Bit Superscaler Microprocessor
Features
s Full militarized QED RM5270 microprocessor
s Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q 133, 150, 200 MHz operating frequencies – Consult Factory for
latest speeds
q 260 Dhrystone2.1 MIPS
q SPECInt95 5.0, SPECfp95 5.3
s High performance system interface compatible with RM5260,
R4600, R4700 and R5000
q 64-bit multiplexed system address/data bus for optimum price/
performance with up to 100 MHz operating frequency
q High performance write protocols maximize uncached write
bandwidth
q Supports clock divisors (2, 3, 4, 5, 6, 7, 8)
q 5V compatible I/O’s
q IEEE 1149.1 JTAG boundary scan
s Integrated on-chip caches
q 16KB instruction - 2 way set associative
q 16KB data - 2 way set associative
q Virtually indexed, physically tagged
q Write-back and write-through on per page basis
q Pipeline restart on first double for data cache misses
s Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)
q 48 dual entries map 96 pages
q Variable page size (4KB to 16MB in 4x increments)
s Integrated secondary cache controller (R5000 compatible)
q Supports 512K or 2MByte block write-through secondary
s High-performance floating point unit
q Single cycle repeat rate for common single precision operations
and some double precision operations
q Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q Single cycle repeat rate for single precision combined multiply-
add operation
s MIPS IV instruction set
q Floating point multiply-add instruction increases performance in
signal processing and graphics applications
q Conditional moves to reduce branch frequency
q Index address modes (register + register)
s Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
q I and D cache locking by set
q Optional dedicated exception vector for interrupts
s Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction
q 6 Watts typical at 3.3V 200 MHz
s 208-lead CQFP, cavity-up package (F17)
s 208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
s 179-pin PGA package (Future Product) (P10)
BLOCK DIAGRAM
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5270 REV 1 12/22/98

1 Page





5270 pdf, ピン配列
Package Information – "F17" – CQFP 208 Leads
1.131 (28.727) SQ
1.109 (28.169) SQ
53
52
104
105
1.009 (25.63)
.9998 (25.37)
51 Spaces at .0197
(51 Spaces at .50)
1
Pin 1 Chamfer
208
Detail "A"
.960 (24.384) SQ
REF
.010R MIN
.010R MIN
.015 (.381)
.009 (.229)
0°±5°
.130 (3.302)
MAX
.100 (2.540)
.080 (2.032)
.035 (.889)
.025 (.635)
.009 (.253)
.007 (.178)
Detail "A"
156
157
.055 (1.397)
REF
.115 (2.921)
MAX
1.331 (33.807)
1.269 (32.233)
.055 (1.397)
.045 (1.143)
Units: Inches (Millimeters)
Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction.
Future Package – "P10" – PGA 179 Pins (Advanced)
Bottom View
Side View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Aeroflex Circuit Technology
1.700
BSC
1.840
1.880
1.700 1.840
BSC 1.880
3
.100
BSC
.018
.050
.221
MAX
SCD5270 REV 1 12/22/98 Plainview NY (516) 694-6700


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[ 5270 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
5270

ACT5270 64-Bit Superscaler Microprocessor

Aeroflex Circuit Technology
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