5270 PDF Data sheet ( 特性 )

部品番号 5270
部品説明 ACT5270 64-Bit Superscaler Microprocessor
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 

Total 5 pages

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5270 Datasheet, 5270 PDF,ピン配置, 機能
64-Bit Superscaler Microprocessor
s Full militarized QED RM5270 microprocessor
s Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q 133, 150, 200 MHz operating frequencies – Consult Factory for
latest speeds
q 260 Dhrystone2.1 MIPS
q SPECInt95 5.0, SPECfp95 5.3
s High performance system interface compatible with RM5260,
R4600, R4700 and R5000
q 64-bit multiplexed system address/data bus for optimum price/
performance with up to 100 MHz operating frequency
q High performance write protocols maximize uncached write
q Supports clock divisors (2, 3, 4, 5, 6, 7, 8)
q 5V compatible I/O’s
q IEEE 1149.1 JTAG boundary scan
s Integrated on-chip caches
q 16KB instruction - 2 way set associative
q 16KB data - 2 way set associative
q Virtually indexed, physically tagged
q Write-back and write-through on per page basis
q Pipeline restart on first double for data cache misses
s Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)
q 48 dual entries map 96 pages
q Variable page size (4KB to 16MB in 4x increments)
s Integrated secondary cache controller (R5000 compatible)
q Supports 512K or 2MByte block write-through secondary
s High-performance floating point unit
q Single cycle repeat rate for common single precision operations
and some double precision operations
q Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q Single cycle repeat rate for single precision combined multiply-
add operation
s MIPS IV instruction set
q Floating point multiply-add instruction increases performance in
signal processing and graphics applications
q Conditional moves to reduce branch frequency
q Index address modes (register + register)
s Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
q I and D cache locking by set
q Optional dedicated exception vector for interrupts
s Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction
q 6 Watts typical at 3.3V 200 MHz
s 208-lead CQFP, cavity-up package (F17)
s 208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
s 179-pin PGA package (Future Product) (P10)
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5270 REV 1 12/22/98

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