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5241 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 5241
部品説明 Quad Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface
メーカ Catalyst Semiconductor
ロゴ Catalyst Semiconductor ロゴ 



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5241 Datasheet, 5241 PDF,ピン配置, 機能
CAT5241
ALOGEN FR
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
FEATURES
LEA D F REETM
s Four linear-taper digitally programmable
potentiometers
s 64 resistor taps per potentiometer
s End to end resistance 2.5k, 10k, 50kor 100k
s Potentiometer control and memory access via
2-wire interface (I2C like)
s Low wiper resistance, typically 80
s Nonvolatile memory storage for up to four wiper
settings for each potentiometer
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 20-lead SOIC and TSSOP packages
s Industrial temperature range
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a 2-wire serial bus (I2C-like). On power-
up, the contents of the first data register (DR0) for each
of the four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC Package (J, W)
TSSOP Package (U, Y)
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
1 20
2 19
3 18
4 17
5 CAT 16
6 5241 15
7 14
8 13
9 12
10 11
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
RH0 RH1 RH2 RH3
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
A0
A1 CONTROL
A2 LOGIC
A3
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
R W0
R W1
R W2
R W3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2011, Rev. J

1 Page





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