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4X16E83V の電気的特性と機能

4X16E83VのメーカーはETCです、この部品の機能は「4 MEG x 16 EDO DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 4X16E83V
部品説明 4 MEG x 16 EDO DRAM
メーカ ETC
ロゴ ETC ロゴ 




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4X16E83V Datasheet, 4X16E83V PDF,ピン配置, 機能
EDO DRAM
4 MEG x 16
EDO DRAM
4X16E43V
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
and package
• 12 row, 10 column addresses (4)
13 row, 9 column addresses (8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Self refresh for low-power data retention
OPTIONS
• Plastic Package
50-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
4K
8K
MARKING
TW
-5
-6
4
8
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
None
IT
NOTE: 1. The “#” symbol indicates signal is active LOW.
PIN ASSIGNMENT (Top View)
50-Pin TSOP
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
VCC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 DQ13
46 DQ12
45 VSS
44 DQ11
43 DQ10
42 DQ9
41 DQ8
40 NC
39 VSS
38 CASL#
37 CASH#
36 OE#
35 NC
34 NC
33 NC/A12
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 VSS
A12 for "8K" version, NC for "4K" version.
Configuration
Refresh
Row Address
Column Addressing
4X16E43V
4 Meg x 16
4K
4K (A0-A11)
1K (A0-A9)
4X16E83V
4 Meg x 16
8K
8K (A0-A12)
512 (A0-A8)
Part Number Example:
MEM4X16E43VTW-5
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
4 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
4X16E43VTW-x
4X16E83VTW-x
x = speed
REFRESH
ADDRESSING
4
8
PACKAGE
400-TSOP
400-TSOP
1

1 Page





4X16E83V pdf, ピン配列
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The device is functionally organized as 4,194,304
locations containing 16 bits each. The 4,194,304
memory locations are arranged in 4,096 rows by 1,024
columns on the MEM4X16E43VTW. During READ or
WRITE cycles, each location is uniquely addressed
via the address bits: 12 row-address bits (A0-A11)
and 10 column-address bits (A0-A9) on the
MEM4X16E43VTW version. In addition, the byte and
word accesses are supported via the two CAS# pins
(CASL# and CASH#).
The CAS# functionality and timing related to ad-
dress and control functions (e.g., latching column
addresses or selecting CBR REFRESH) is such that the
internal CAS# signal is determined by the first external
CAS# signal (CASL# or CASH#) to transition LOW and
4 MEG x 16
EDO DRAM
the last to transition back HIGH. The CAS# functional-
ity and timing related to driving or latching data is such
that each CAS# signal independently controls the asso-
ciated eight DQ pins.
The row address is latched by the RAS# signal, then
the column address is latched by CAS#. This device
provides EDO-PAGE-MODE operation, allowing for fast
successive data operations (READ, WRITE or READ-
MODIFY-WRITE) within a given row.
The 4 Meg x 16 DRAM must be refreshed periodi-
cally in order to retain stored data.
DRAM ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. Use of both
CAS# signals results in a word access via the 16 I/O pins
(DQ0-DQ15). Using only one of the two signals results
in a BYTE access cycle. CASL# transitioning LOW se-
lects an access cycle for the lower byte (DQ0-DQ7), and
CASH# transitioning LOW selects an access cycle for
RAS#
WORD WRITE
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
STORED
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
UPPER BYTE
(DQ8-DQ15)
OF WORD
0 X 1 11
1 X 0 00
0 X 1 11
1 X 0 00
0 X 1 11
0 X 1 11
0 X 1 11
0 X 1 11
X
X
X
X
X
X
X
X
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON?T CARE)
Figure 1
WORD and BYTE WRITE Example
1
0
1
0
1
1
1
1
3


3Pages


4X16E83V 電子部品, 半導体
EDO PAGE MODE (continued)
two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for tOEHC thereafter. This will disable
the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#
transitions HIGH and then bring OE# HIGH for a
minimum of tOEP anytime during the CAS# HIGH
period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again (see Figure 3). During other
cycles, the outputs are disabled at tOFF time after RAS#
and CAS# are HIGH or at tWHZ after WE# transitions
LOW. The tOFF time is referenced from the rising edge
of RAS# or CAS#, whichever occurs last. WE# can also
perform the function of disabling the output drivers
under certain conditions, as shown in Figure 4.
EDO-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE
operation.
DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all rows in the
4 Meg x 16 DRAM array at least once every 64ms (8,192
4 MEG x 16
EDO DRAM
rows for 8 or 4,096 rows for 8). The recommended
procedure is to execute 4,096 CBR REFRESH cycles,
either uniformly spaced or grouped in bursts, every
64ms. The MEM4X16E43VTW refreshes one row for every
CBR cycle. For either device, executing 4,096 CBR
cycles will refresh the entire device. The CBR REFRESH
will invoke the internal refresh counter for automatic
RAS# addressing. Alternatively, RAS#-ONLY REFRESH
capability is inherently provided. However, with this
method, only one row is refreshed on each cycle. JEDEC
strongly recommends the use of CBR REFRESH for this
device.
The self refresh mode is also available.
The self refresh feature is initiated by
performing a CBR Refresh cycle and holding RAS# low
for the specified tRASS. The self refresh mode allows
the user the choice of a fully static, low-power data
retention mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25µs per cycle, when
using a distributed CBR refresh. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of t RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh, however, if the controller is
using RAS# only or burst CBR refresh then a burst
refresh using t RC (MIN) is required.
6

6 Page



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部品番号部品説明メーカ
4X16E83V

4 MEG x 16 EDO DRAM

ETC
ETC
4X16E83VTW-6

4 MEG x 16 EDO DRAM

ETC
ETC


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