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PDF 49FCT805 Data sheet ( Hoja de datos )
| Número de pieza | 49FCT805 | |
| Descripción | FAST CMOS BUFFER/CLOCK DRIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805/A
IDT49FCT806/A
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 700ps (max.)
• Low duty cycle distortion < 1ns (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• Rail-to-rail output voltage swing
• High drive: -24mA IOH, 64mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• ‘Heartbeat’ monitor output
• Available in DIP, SOIC, SSOP (805 only), QSOP (805
only), Cerpack and LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT49FCT805/A and IDT49FCT806/A are clock
drivers built using advanced dual metal CMOS technology.
The IDT49FCT805/A is a non-inverting clock driver and the
IDT49FCT806/A is an inverting clock driver. Each device
consists of two banks of drivers. Each bank drives five output
buffers from a standard TTL compatible input. The devices
feature a "heartbeat" monitor for diagnostics and PLL driving.
The MON output is identical to all other outputs and complies
with the output specifications in this document. The
IDT49FCT805/A and IDT49FCT806/A offer low capacitance
inputs with hysteresis. Rail-to-rail output swing improves
noise margin and allows easy interface with CMOS inputs.
FUNCTIONAL BLOCK DIAGRAMS
IDT49FCT805
OEA
INA 5 OA1-OA5
INB 5 OB1-OB5
IDT49FCT806
OEA
INA
INB
5 OA1-OA5
5 OB1-OB5
OEB
MON
2574 drw 01
OEB
MON
2574 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
9.1
SEPTEMBER 1996
DSC-2574/10
1
1 page  
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805/806
IDT49FCT805A/806A
Com'l. Mil. Com'l. Mil.
Symbol
Parameter
tPLH Propagation Delay
tPHL INA to OAn, INB to OBn
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
1.5
Max.
5.6
Min.(2)
1.5
Max.
6.3
Min.(2)
1.5
Max.
5.3
Min.(2)
1.5
Max.
6.0
Unit
ns
tR Output Rise Time
— 1.5 — 1.5 — 1.5 — 1.5 ns
tF Output Fall Time
— 1.5 — 1.5 — 1.5 — 1.5 ns
tSK(o) Output skew: skew between outputs of all
banks of same package (inputs tied together)
— 0.7 — 0.9 — 0.7 — 0.9 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output (|tPHL-tPLH|)
— 1.0 — 1.1 — 1.0 — 1.1 ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
— 1.5 — 1.5 — 1.5 — 1.5 ns
tPZL Output Enable Time
tPZH OEA to OAn, OEB to OBn
1.5 8.0 1.5 8.5 1.5 8.0 1.5 8.5 ns
tPLZ Output Disable Time
tPHZ OEA to OAn, OEB to OBn
1.5 7.0 1.5 7.5 1.5 7.0 1.5 7.5 ns
NOTES:
2574 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.1 5
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