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PDF 5962R9582501VEC Data sheet ( Hoja de datos )
| Número de pieza | 5962R9582501VEC | |
| Descripción | Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer | |
| Fabricantes | Intersil Corporation | |
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HS-54C138RH
February 1996
Radiation Hardened
3-Line to 8-Line Decoder/Demultiplexer
Features
• Devices QML Qualified in Accordance With
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95825 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Total Dose 1 x 105 RAD (Si)
- Latch-Up Immune > 1 x 1012 RAD (Si)/s
• Multiple Input Enable for Easy Expansion
• Single Power Supply +5V
• Outputs Active Low
• Low Standby Power (0.5mW Max at +5V)
• High Noise Immunity
• Equivalent to Sandia SA2995
• Bus Compatible with Intersil Rad-Hard 80C85RH
• Full Military Temperature Range -55oC to +125oC
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 VDD
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
Description
The Intersil HS-54C138RH is a radiation hardened 3- to 8-line
decoder fabricated using a radiation hardened EPI-CMOS pro-
cess. It features low power consumption, high noise immunity,
and high speed. Also featured are pin and function compatibility
with the 54LS138 industry standard part. The HS-54C138RH is
ideally suited for high speed memory chip select address
decoding. It is intended for use with the Intersil HS-80C85RH
radiation hardened microprocessor, but it can also be utilized as
a demultiplexer in any low power rad-hard application.
The HS-54C138RH contains a one of eight binary decoder.
A three bit binary input is used to select and activate each of
the eight outputs, provided the three chip enable inputs are
also present (see truth table).
The HS-54C138RH has an on-chip enable gate. The active
high (G1) and both active low (G2A, G2B) inputs are Anded
together to provide a single enable input to the device. The
use of both active high and active low inputs minimizes the
need for external gates when expanding a system.
A
B
C
G2A
G2B
G1
Y7
GND
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Ordering Information
PART NUMBER
5962R9582501QEC
5962R9582501QXC
5962R9582501VEC
5962R9582501VXC
HS1-54C138RH/SAMPLE
HS9-54C138RH/SAMPLE
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
Sample
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518053
File Number 3037.2
1 page  
HS-54C138RH
Typical applications include systems which require multiple
input/output ports and memories. When the HS-54C138RH
is enabled one of the eight outputs will go low. This output
can be used to select a particular device or a group of
devices. The HS-54C138RH can also be cascaded to
provide an enabling scheme for larger systems and allow
one decoder to control eight other decoders as in Figure 1.
Figure 2 shows a configuration that can be used to enable
multiple I/O ports or memory devices. Up to 24 memory
devices or I/O ports can be controlled using this circuit.
For demultiplexer operation, one of the three enable inputs is
used as the data input while the other two inputs are enable.
The transmitted data is distributed to the proper output as
determined by the 3-line select inputs. See Figure 3.
TO OTHER
DEVICES
SELECT B
SELECT A
ENABLE
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
“1” “0”
ENABLE
“1” “0”
ENABLE
“1” “0”
ENABLE
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
FIGURE 1
EN
EN
EN A4 A3
A2 A1 A0
G1 G2B G2A
CBA
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
G1 G2B G2A
CBA
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
G1 G2B G2A
CBA
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
PORT NUMBERS OR CHIP SELECTS
FIGURE 2
DATA
INPUT
EN
EN
G1 G2B G2A
CBA
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
FIGURE 3
5
Spec Number 518053
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 5962R9582501VEC.PDF ] | |
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