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5962F9563501QYC の電気的特性と機能

5962F9563501QYCのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Real Time Express Microcontroller」です。


製品の詳細 ( Datasheet PDF )

部品番号 5962F9563501QYC
部品説明 Radiation Hardened Real Time Express Microcontroller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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5962F9563501QYC Datasheet, 5962F9563501QYC PDF,ピン配置, 機能
Data Sheet
HS-RTX2010RH
March 2000
File Number 3961.3
Radiation Hardened Real Time Express™
Microcontroller
The HS-RTX2010RH is a radiation-hardened 16-bit
microcontroller with on-chip timers, an interrupt controller, a
multiply-accumulator, and a barrel shifter. It is particularly
well suited for space craft environments where very high
speed control tasks which require arithmetically intensive
calculations, including floating point math to be performed in
hostile space radiation environments.
This processor incorporates two 256-word stacks with
multitasking capabilities, including configurable stack
partitioning and over/underflow control.
Instruction execution times of one or two machine cycles are
achieved by utilizing a stack oriented, multiple bus
architecture. The high performance ASIC Bus, which is
unique to the RTX product, provides for extension of the
microcontroller architecture using off-chip hardware and
application specific I/O devices.
RTX Microcontrollers support the C and Forth programming
languages. The advantages of this product are further
enhanced through third party hardware and software support.
Combined, these features make the HS-RTX2010RH an
extremely powerful processor serving numerous
applications in high performance space systems. The
HS-RTX2010RH has been designed for harsh space
radiation environments and features outstanding Single
Event Upset (SEU) resistance and excellent total dose
response.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95635. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(oC)
5962F9563501QXC HS8-RTX2010RH-8
55 to 125
5962F9563501QYC HS9-RTX2010RH-8
55 to 125
5962F9563501V9A HS0-RTX2010RH-Q
25
5962F9563501VXC HS8-RTX2010RH-Q
55 to 125
5962F9563501VYC HS9-RTX2010RH-Q
55 to 125
HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto 55 to 125
HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto 55 to 125
Features
• Electrically Screened to SMD # 5962-95635
• QML Qualified per MIL-PRF-38535 Requirements
• Fast 125ns Machine Cycle
• 1.2µM TSOS4 CMOS/SOS Process
• Total Dose Capability . . . . . . . . . . . . . . . . . . 300KRad(Si)
• Single Event Upset Critical LET . . . . . . . >120MeV/mg/cm2
• Single Event Upset Error Rate . . . . <1 x 10-10 Errors/Bit-Day
(Note)
• -55oC - 125oC, 5V ±10% Operation
• Single Cycle Instruction Execution
• Fast Arithmetic Operations
- Single Cycle 16-Bit Multiply
- Single Cycle 16-Bit Multiply Accumulate
- Single Cycle 32-Bit Barrel Shift
- Hardware Floating Point Support
• C Software Development Environment
• Direct Execution of Fourth Language
• Single Cycle Subroutine Call/Return
• Four Cycle Interrupt Latency
• On-Chip Interrupt Controller
• Three On-Chip 16-Bit Timer/Counters
• Two On-Chip 256 Word Stacks
• ASIC Bus™ for Off-Chip Architecture Extension
• 1 Megabyte Total Address Space
• Word and Byte Memory Access
• Fully Static Design - DC to 8MHz Operation
• 84 Lead Quad Flat Package or 85 Pin Grid Array
• Third Party Software and Hardware Development Systems
NOTE: Single Event Upset error rates are Adams 10% worst case
environment under worst case conditions for upset.
Applications
• Space Systems Embedded Control
• Digital Filtering
• Image Processing
• Scientific Instrumentation
• Optical Systems
• Control Systems
• Attitude/Orbital Control
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
Real Time Express™, RTX™, and ASIC Bus™ are trademarks of Intersil Corporation.

1 Page





5962F9563501QYC pdf, ピン配列
Pinouts (Continued)
HS-RTX2010RH
HS9-RTX2010RH
(LEAD LENGTH NOT TO SCALE) SEE INTERSIL OUTLINE R84.A
RESET
WAIT
ICLK
GR/W
GIO
GD15
GD14
GD13
GND
GD12
GD11
GD10
GD09
GD08
GD07
VDD
GD06
GD05
GD04
GD03
GND
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HS-RTX2010RH
TOP VIEW
74 MD08
73 VDD
72 MD07
71 MD06
70 MD05
69 GND
68 MD04
67 MD03
66 MD02
65 MD01
64 MD00
63 MR/W
62 PCLK
61 BOOT
60 NEW
59 UDS
58 LDS
57 GND
56 MA19
55 MA18
54 MA17
NOTE: An overbar on a signal name represents an active LOW signal.
PGA And CQFP
Pin/Signal Assignments
CQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PGA
PIN
C6
A6
A5
B5
C5
A4
B4
A3
A2
B3
A1
B2
C2
B1
C1
D2
D1
E3
E2
E1
F2
F3
G3
SIGNAL
NAME
GA02
TCLK
INTA
NMI
INTSUP
VDD
EI1
EI2
EI3
EI4
EI5
RESET
WAIT
ICLK
GR/W
GIO
GD15
GD14
GD13
GND
GD12
GD11
GD10
TYPE
Output; Address Bus
Output
Output
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Ground
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
3
PGA And CQFP
Pin/Signal Assignments (Continued)
CQFP
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PGA
PIN
G1
G2
F1
H1
H2
J1
K1
J2
L1
K2
K3
L2
L3
K4
L4
J5
K5
L5
K6
J6
J7
L7
K7
SIGNAL
NAME
GD09
GD08
GD07
VDD
GD06
GD05
GD04
GD03
GND
GD02
GD01
GD00
MA01
MA02
MA03
MA04
MA05
MA06
MA07
MA08
GND
MA09
MA10
TYPE
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Power
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Ground
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Ground
Output; Address Bus
Output; Address Bus


3Pages


5962F9563501QYC 電子部品, 半導体
HS-RTX2010RH
Timing Diagrams
ICLK
t11
TCLK
WAIT
t15
t1
t2 t3
t13
t19
t12
t5
t20
t4
t5
t4
PCLK
(NOTE 1)
PCLK
(NOTE 2)
GIO
(NOTE 3)
t17 t16
t51
t20
t50
NOTES:
1. NORMAL CYCLE: This waveform describes a normal PCLK cycle and a PCLK cycle with a Wait state.
2. EXTENDED CYCLE: This waveform describes a PCLK cycle for a USER memory access or an external ASIC Bus read cycle when the CYCEXT
bit or ARCE bit is set.
3. EXTENDED CYCLE: This waveform describes a GIO cycle for an external ASIC Bus read when the ARCE bit is set.
4. An active HIGH signal on the RESET input is guaranteed to reset the processor if its duration is greater than or equal to 4 rising edges of ICLK
plus 1/2 ICLK cycle setup and hold times. If the RESET input is active for less than four rising edges of ICLK, the processor will not reset.
FIGURE 2. CLOCK AND WAIT TIMING
EI5 - EI3
t6
t7 t8
FIGURE 3. TIMER/COUNTER TIMING
6

6 Page



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部品番号部品説明メーカ
5962F9563501QYC

Radiation Hardened Real Time Express Microcontroller

Intersil Corporation
Intersil Corporation


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