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5962-9750601HXC の電気的特性と機能

5962-9750601HXCのメーカーはAnalog Devicesです、この部品の機能は「Quad-SHARC DSP Multiprocessor Family」です。


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部品番号 5962-9750601HXC
部品説明 Quad-SHARC DSP Multiprocessor Family
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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5962-9750601HXC Datasheet, 5962-9750601HXC PDF,ピン配置, 機能
a
Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
PERFORMANCE FEATURES
ADSP-21060 Core Processor (. . . ؋4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Twelve 40 Mbyte/s Link Ports (Three per SHARC)
Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC)
One 40 Mbit/s Common Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size
Cavity Up or Down, Configurable
Low Profile, 0.160" Height
Hermetic
25 Mil (0.65 mm) Lead Pitch
29 Grams (typical)
JC = 0.36؇C/W
FUNCTIONAL BLOCK DIAGRAM
CPA
SPORT 1 SHARC_A
TDI (ID2-0 = 1)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
CPA
SHARC_B SPORT 1
(ID2-0 = 2)
AD14060/
AD14060L
SHARC BUS (ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1.2, DMAG1.2)
CPA SHARC_D
SPORT 1 (ID2-0 = 4)
TDO
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SHARC_C
CPA
(ID2-0 = 3)
SPORT 1
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
The AD14060/AD14060L modules have the highest perfor-
mance —density and lowest cost—performance ratios of any in
their class. They are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multi-
processing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997

1 Page





5962-9750601HXC pdf, ピン配列
INTERNAL
MEMORY
SPACE
(INDIVIDUAL
SHARCs)
MULTIPROCESSOR
MEMORY SPACE
INTERNAL
TO AD14060
EXTERNAL
TO AD14060
IOP REGISTERS
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
OF SHARC_A
ID=001
INTERNAL MEMORY SPACE
OF SHARC_B
ID=010
INTERNAL MEMORY SPACE
OF SHARC_C
ID=011
INTERNAL MEMORY SPACE
OF SHARC_D
ID=100
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
BROADCAST WRITE
TO ALL
ADSP-2106xs
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
EXTERNAL
MEMORY
SPACE
Figure 2. AD14060/AD14060L Memory Map
AD14060/AD14060L
BANK 0
DRAM
(OPTIONAL)
0x0040 0000
MS0
BANK 1
MS1
BANK 2
MS2
BANK 3
NONBANKED
MS3
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
0xFFFF FFFF
1X CLOCK
SYSTEM EXPANSION
CLKIN
RESET
RPBA
CPA
SHARC_A
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
SHARC_B
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
BOOTSELECT A
BOOTSELECT BCD
DMAR1,2
DMAG1,2
AD14060/AD14060L
(QUAD PROCESSOR
CLUSTER)
SPORT0
FLAG1
JTAG
SHARC_D
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
SHARC_C
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
ADDR31-0
DATA47-0
RD
WR
ACK
MS3-0
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
BR1-6
Figure 3. Complete Shared Memory Multiprocessing System
REV. A
–3–


3Pages


5962-9750601HXC 電子部品, 半導体
AD14060/AD14060L
Serial Ports
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices. Each
SHARC has two serial ports. The AD14060/AD14060L provides
direct access to Serial Port 1 of each SHARC. Serial Port 0
is bused together in common to each SHARC, and brought
off-module.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s. Inde-
pendent transmit and receive functions provide more flexible
communications. Serial port data can be automatically trans-
ferred to and from on-SHARC memory via DMA, and each of
the serial ports offers time division multiplexed (TDM) multi-
channel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit modes
as well as optional µ-law or A-law companding. Serial port clocks
and frame syncs can be internally or externally generated.
Program Booting
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers four options for program booting: 1) from an 8-bit
EPROM; 2) from a host processor; 3) through the link ports;
and 4) no-boot. In no-boot mode, the SHARC starts executing
instructions from address 0x0040 0004 in external memory.
The boot mode is selected by the state of the following signals:
BMS, EBOOT, and LBOOT.
On the AD14060/AD14060L, SHARC_A’s boot mode is sepa-
rately controlled, while SHARCs B, C, and D are controlled as
a group. With this flexibility, the AD14060/AD14060L can be
configured to boot in any of the following methods.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 will be in
the idle state and the BRx bus request lines will be deasserted.
The host must assert the HBR input and boot each ADSP-21060
by asserting its CS pin and downloading instructions.
Multiprocessor EPROM Booting
There are two methods of booting the multiprocessor system
from an EPROM.
SHARC_A Is Booted, Which Then Boots the Others. The
EBOOT pin on the SHARC_A must be set high for EPROM
booting. All other ADSP-21060s should be configured for host
booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which
leaves them in the idle state at start-up and allows SHARC_A
to become bus master and boot itself. Only the BMS pin of
SHARC_A is connected to the chip select of the EPROM.
When SHARC_A has finished booting, it can boot the re-
maining ADSP-21060s by writing to their external port DMA
buffer 0 (EPB0) via multiprocessor memory space.
All ADSP-21060s Boot in Turn From a Single EPROM.
The BMS signals from each ADSP-21060 may be wire-ORed
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority. When
the last one has finished booting, it must inform the others
(which may be in the idle state) that program execution can begin.
Multiprocessor Link Port Booting
Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting.
To simultaneously boot all of the ADSP-21060s, a parallel
common connection is available through Link Port 4 on each of
the processors. Or, using the daisy chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the Link Assignment Register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.
Multiprocessor Booting From External Memory
If external memory contains a program after reset, then
SHARC_A should be set up for no boot mode; it will begin ex-
ecuting from address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s may be booted
by SHARC_A if they are set up for host booting, or they can
begin executing out of external memory if they are set up for no
boot mode. Multiprocessor bus arbitration will allow this booting
to occur in an orderly manner.
Host Processor Interface
The AD14060/AD14060L’s host interface allows for easy con-
nection to standard microprocessor buses, both 16-bit and 32-
bit, with little additional hardware required. Asynchronous
transfers at speeds up to the full clock rate of the module are
supported. The host interface is accessed through the AD14060/
AD14060L external port and is memory-mapped into the uni-
fied address space. Four channels of DMA are available for the
host interface; code and data transfers are accomplished with
low software overhead.
The host processor requests the AD14060/AD14060L’s external
bus with the host bus request (HBR), host bus grant (HBG),
and ready (REDY) signals. The host can directly read and write
the internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
Direct Memory Access (DMA) Controller
The SHARCs on-chip DMA control logic allows zero-overhead
data transfers without processor intervention. The DMA con-
troller operates independently and invisibly to each SHARCs
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions.
DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA trans-
fers between external memory and external peripheral devices are
another option. External bus packing to 16-, 32- or 48-bit words
is performed during DMA transfers.
Ten channels of DMA are available on the SHARCs—two via
the link ports, four via the serial ports, and four via the processor’s
external port (for either host processor, other SHARCs, memory,
or I/O transfers). Four additional link port DMA channels are
shared with serial port 1 and the external port. Programs can be
downloaded to the SHARCs using DMA transfers. Asynchronous
off-module peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other
DMA features include interrupt generation upon completion of
DMA transfers and DMA chaining for automatic linked DMA
transfers.
–6– REV. A

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部品番号部品説明メーカ
5962-9750601HXC

Quad-SHARC DSP Multiprocessor Family

Analog Devices
Analog Devices


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