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5962-9736101QYA の電気的特性と機能

5962-9736101QYAのメーカーはCypress Semiconductorです、この部品の機能は「16K/32K x 9 Deep Sync FIFOs」です。


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部品番号 5962-9736101QYA
部品説明 16K/32K x 9 Deep Sync FIFOs
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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5962-9736101QYA Datasheet, 5962-9736101QYA PDF,ピン配置, 機能
CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 35 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
Logic Block Diagram D0 8
INPUT
REGISTER
WCLK WEN1 WEN2/LD
WRITE
CONTROL
WRITE
POINTER
RS
RESET
LOGIC
RAM
ARRAY
16K x 9
32K x 9
THREE-STATE
OUTPUT REGISTER
Q0 8
OE
Pin Configuration PLCC/LCC
Top View
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
EF
PAE
PAF
FF
READ
CONTROL
RCLK REN1 REN2
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 32 31 30
5 29
6 28
7 27
8 CY7C4261 26
9
10
CY7C4271
25
24
11 23
12 22
13 21
14 15 16 17 18 19 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
TQFP
Top View
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4
CY7C4261
21
5 CY7C4271 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06015 Rev. *B
Revised August 21, 2003

1 Page





5962-9736101QYA pdf, ピン配列
CY7C4261
CY7C4271
Density
Package
CY7C4261
16K × 9
32-pin PLCC,TQFP
CY7C4271
32K × 9
32-pin
LCC,PLCC,TQFP
Architecture
The CY7C4261/71 consists of an array of 16K to 32K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q08) go LOW tRSF after the rising
edge of RS. In order for the FIFO to reset to its default state, a falling
edge must occur on RS and the user must not read or write while RS
is LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH, and
FF is active HIGH, data present on the D08 pins is written into the
FIFO on each rising edge of the WCLK signal. Similarly, when the
REN1 and REN2 signals are active LOW and EF is active HIGH, data
in the FIFO memory will be presented on the Q08 outputs. New data
will be presented on each rising edge of RCLK while REN1 and
REN2 are active. REN1 and REN2 must set up tENS before RCLK
for it to be a valid read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q08
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q08 outputs after tOE. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q08 outputs even
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, WEN2/LD
can be used to access the four 8-bit offset registers contained in the
CY7C4261/71 for writing or reading data to these registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and full
offset MSB register, respectively, when WEN2/LD and WEN1 are
LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD
and WEN1 are LOW writes data to the empty LSB register again.
Figure 1 shows the registers sizes and default values for the various
device types.
16K × 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
32K × 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
5
08
6
0
(MSB)
000000
(MSB)
0000000
87
0
Full Offset (LSB) Reg
Default Value = 007h
87
0
Full Offset (LSB) Reg
Default Value = 007h
8
5
08
6
0
(MSB)
000000
(MSB)
0000000
Figure 1. Offset Register Location and Default Values
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read and
write operation. The next time WEN2/LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) (PAF) states are deter-
mined by their corresponding offset registers and the
difference between the read and write pointers.
Document #: 38-06015 Rev. *B
Page 3 of 18


3Pages


5962-9736101QYA 電子部品, 半導体
CY7C4261
CY7C4271
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ....................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................... −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................−0.5V to VCC + 0.5V
DC Input Voltage..........................................0.5V to Vcc+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial[5]
Military
Ambient Temperature
0°C to +70°C
40°C to +85°C
55°C to +125°C
VCC
5V ± 10%
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range[6]
7C4261/7110 7C4261/7115 7C4261/7125 7C4261/7135
Parameter
Description
Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
2.4
V
IOH = 2.0 mA
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage
(comm./ind.)
2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V
VIH Input HIGH Voltage
(military)
2.2 VCC 2.2 VCC 2.2 VCC 2.2 VCC V
VIL
IIX
IOZL
IOZH
ICC1[7]
ISB[8]
Input LOW Voltage
Input Leakage Current VCC = Max.
Output OFF,
High Z Current
OE > VIH,
VSS < VO< VCC
Active Power Supply
Current
Com’l
Ind/Mil
Average Standby
Current
Com’l
Ind/Mil
0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 V
10 +10 10 +10 10 +10 10 +10 µA
10 +10 10 +10 10 +10 10 +10 µA
35 35 35 35 mA
40 40 40 40 mA
10 10 10 10 mA
15 15 15 15 mA
Capacitance[9]
Parameter
Description
CIN Input Capacitance
COUT
Output Capacitance
AC Test Loads and Waveforms[10, 11]
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
5
7
Unit
pF
pF
5V
OUTPUT
R11.1KW
INCLUDING CL
JIG AND
SCOPE
R2
680
3.0V
GND
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
3 ns
Equivalent to: THÉVENIN EQUIVALENT
420
Notes:
OUTPUT
1.91V
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. TA is the “instant on” case temperature.
6. See the last page of this specification for Group A subgroup testing information.
7. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20 Mhz, while data inputs switch
at 10 MHz. Outputs are unloaded. ICC1(typical) = (20 mA + (freq – 20 MHz) * (0.7 mA/MHz)).
8. All inputs = VCC – 0.2V, except WCLK and RCLK (which are switching at frequency = 20 MHz). All outputs are unloaded.
9. Tested initially and after any design or process changes that may affect these parameters.
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
Document #: 38-06015 Rev. *B
Page 6 of 18

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部品番号部品説明メーカ
5962-9736101QYA

16K/32K x 9 Deep Sync FIFOs

Cypress Semiconductor
Cypress Semiconductor


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