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PDF 5962-9559801MRA Data sheet ( Hoja de datos )
| Número de pieza | 5962-9559801MRA | |
| Descripción | 250 MHz Demodulating Logarithmic Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
250 MHz Demodulating
Logarithmic Amplifier
AD641
FEATURES
Logarithmic Amplifier Performance
Usable to 250 MHz
44 dB Dynamic Range
؎2.0 dB Log Conformance
37.5 mV/dB Voltage Output
Stable Slope and Intercepts
2.0 nV/√Hz Input Noise Voltage
50 V Input Offset Voltage
Low Power
؎5 V Supply Operation
9 mA (+VS), 35 mA (–VS) Quiescent Current
Onboard Resistors
Onboard 10؋ Attenuator
Dual Polarity Current Outputs
Direct Coupled Differential Signal Path
APPLICATIONS
IF/RF Signal Processing
Received Signal Strength Indicator (RSSI)
High Speed Signal Compression
High Speed Spectrum Analyzer
ECM/Radar
PRODUCT DESCRIPTION
The AD641 is a 250 MHz, demodulating logarithmic amplifier
with an accuracy of ± 2.0 dB and 44 dB dynamic range. The
AD641 uses a successive detection architecture to provide an
output current that is logarithmically proportional to its input
voltage. The output current can be converted to a voltage using
one of several on-chip resistors to select the slope. A single
AD641 provides up to 44 dB of dynamic range at speeds up to
250 MHz, and two cascaded AD641s together can provide
58 dB of dynamic range at speeds up to 250 MHz. The AD641
is fully stable and well characterized over either the industrial or
military temperature ranges.
The AD641 is not a logarithmic building block, but rather a
complete logarithmic solution for compressing and measuring
wide dynamic range signals. The AD641 is comprised of five
stages and each stage has a full wave rectifier, whose current
depends on the absolute value of its input voltage. The output
of these stages are summed together to provide the demodulated
output current scaled at 1 mA per decade (50 µA/dB).
Without utilizing the 10× input attenuator, log conformance of
2.0 dB is maintained over the input range –44 dBm to 0 dBm.
The attenuator offers the most flexibility without significantly
impacting performance.
PIN CONFIGURATIONS
20-Lead Plastic DIP (N)
20-Lead Cerdip (Q)
–INPUT 1
20 +INPUT
ATN LO 2
19 ATN OUT
ATN COM 3
18 CKT COM
ATN COM 4
17 RG1
ATN IN
BL1
–VS
5 AD641 16 RG0
6 TOP VIEW 15 RG2
(Not to Scale)
7 14 LOG OUT
ITC 8
13 LOG COM
BL2 9
–OUTPUT 10
12 +VS
11 +OUTPUT
20-Lead PLCC (P)
ATN COM 4
ATN IN 5
BL1 6
–VS 7
ITC 8
3 2 1 20 19
PIN 1
18 CKT COM
IDENTIFIER
AD641
TOP VIEW
17 RG1
16 RG0
(Not to Scale)
15 RG2
14 LOG OUT
9 10 11 12 13
The 250 MHz bandwidth and temperature stability make this
product ideal for high speed signal power measurement in RF/
IF systems. ECM/Radar and Communication applications are
routinely in the 100 MHz–180 MHz range for power measure-
ment. The bandwidth and accuracy, as well as dynamic range,
make this part ideal for high speed, wide dynamic range signals.
The AD641 is offered in industrial (–40°C to +85°C) and mili-
tary (–55°C to +125°C) package temperature ranges. Industrial
versions are available in plastic DIP and PLCC; MIL versions
are packaged in cerdip.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
Typical AC Performance Characteristics–AD641
–2.25
–2.00
–1.75
–1.50
50MHz
150MHz
190MHz
210MHz
250MHz
–1.25
–1.00
–0.75
–0.50
–0.25
0.00
0.25
–52 –48 –44 –40 –36 –32 –28 –24 –20 –16 –12 –8 –4 0 2
INPUT LEVEL – dBm
Figure 10. AC Response at 50 MHz, 150 MHz, 190 MHz,
210 MHz at 250 MHz, vs. dBm Input (Sinusoidal Input)
–2.00
–1.75
–1.50
+125؇C
5
+125؇C 4
+25؇C
3
–1.25
+25؇C
–55؇C 2
–1.00
–0.75
–55؇C
ERROR
–0.50
–0.25
+125؇C
–0.00
OUTPUT
+125؇C
+25؇C
–55؇C
0.25
+25؇C
–55؇C
0.50
–52 –48 –44 –40 –36 –32 –28 –24 –20 –16 –12 –8 –4
INPUT LEVEL – dBm
1
0
–1
–2
–3
–4
–5
02
Figure 13. Logarithmic Response and Linearity at
200 MHz, TA for TA = –55°C, +25°C, +125°C
87.5
85.0
82.5
80.0
77.5
75.0
72.5
70.0
50
100 150 170 190 210 230 250
INPUT FREQUENCY – MHz
Figure 11. Intercept Level (dBm) vs. Frequency (Cascaded
AD641s—Sinusoidal Input)
1.0
0.95
0.90
0.85
0.80
0.75
50
150 190
210
INPUT FREQUENCY – MHz
250
Figure 14. Slope Current, IY, vs. Input Frequency
5µs
100
90
5µs
Figure 12. Baseband Pulse Response of Single AD641,
Inputs of 1 mV, 10 mV and 100 mV
10
0%
20mV
20mV
Figure 15. Baseband Pulse Response of Cascaded AD641s
at Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV
REV. C
–5–
5 Page 
AD641
Unused pins (excluding Pins 8, 10 and 11) such as the attenua-
tor and applications resistors should be grounded close to the
package edge. BL1 (Pin 6) and BL2 (Pin 9) are internal bias
lines a volt or two above the –VS node; access is provided solely
for the addition of decoupling capacitors, which should be con-
nected exactly as shown (not all of them connect to the ground).
Use low impedance ceramic 0.1 µF capacitors (for example,
Erie RPE113-Z5U-105-K50V). Ferrite beads may be used
instead of supply decoupling resistors in cases where the supply
voltage is low.
Active Current-to-Voltage Conversion
The compliance at LOG OUT limits the available output volt-
age swing. The output of the AD641 may be converted to a
larger, buffered output voltage by the addition of an operational
amplifier connected as a current-to-voltage (transresistance)
stage, as shown in Figure 21. Using a 2 kΩ feedback resistor
(R2) the 50 µA/dB output at LOG OUT is converted to a volt-
age having a slope of +100 mV/dB, that is, 2 V per decade.
This output ranges from roughly –0.4 V for zero signal inputs
to the AD641, crosses zero at a dc input of precisely +1 mV
(or –1 mV) and is +4 V for a dc input of 100 mV. A passive
prefilter, formed by R1 and C1, minimizes the high frequency
energy conveyed to the op amp. The corner frequency is here
shown as 10 MHz. The AD846 is recommended for this appli-
cation because of its excellent performance in transresistance
modes. Its bandwidth of 35 MHz (with the 2 kΩ feedback resis-
tor) will exceed the baseband response of the system in most
applications. For lower bandwidth applications other op amps
and multipole active filters may be substituted.
Effect of Frequency on Calibration
The slope and intercept of the AD641 are calibrated during
manufacture using a 2 kHz square wave input. Calibration
depends on the gain of each stage being 10 dB. When the input
frequency is an appreciable fraction of the 350 MHz bandwidth
of the amplifier stages, their gain becomes less precise and the
logarithmic slope and intercept are no longer as calibrated.
Figure 10 shows the averaged output current versus input level
at 50 MHz, 150 MHz, 190 MHz, 210 MHz, and 250 MHz.
Figure 11 shows the absolute error in the response at 200 MHz
and at temperatures of –55°C, +25°C and +125°C. Figure 12
shows the variation in the slope current, and Figure 13 shows
the variation in the intercept level (sinusoidal input) versus
frequency.
If absolute calibration is essential, or some other value of slope
or intercept is required, there will usually be some point in the
user’s system at which an adjustment may be easily introduced.
For example, the 5% slope deficit at 50 MHz (see Figure 12)
may be restored by a 5% increase in the value of the load resis-
tor in the passive loading scheme shown in Figure 24, or by
inserting a trim potentiometer of 100 Ω in series with the feed-
back resistor in the scheme shown in Figure 21. The intercept
can be adjusted by adding or subtracting a small current to the
output. Since the slope current is 1 mA/decade, a 50 µA incre-
ment will move the intercept by 1 dB. Note that any error in
this current will invalidate the calibration of the AD641. For
example, if one of the 5 V supplies were used with a resistor to
generate the current to reposition the intercept by 20 dB, a
± 10% variation in this supply will cause a ± 2 dB error in the
absolute calibration. Of course, slope calibration is unaffected.
Source Resistance and Input Offset
The bias currents at the signal inputs (Pins 1 and 20) are typi-
cally 7 µA. These flow in the source resistances and generate
input offset voltages which may limit the dynamic range because
the AD641 is direct coupled and an offset is indistinguishable
from a signal. It is good practice to keep the source resistances
as low as possible and to equalize the resistance seen at each
input. For example, if the source resistance to Pin 20 is 100 Ω, a
compensating resistor of 100 Ω should be placed in series with
Pin 1. The residual offset is then due to the bias current offset,
which is typically under 1 µA, causing an extra offset uncertainty
of 100 µV in this example. For a single AD641 this will rarely be
troublesome, but in some applications it may need to be nulled
out, along with the internal voltage offset component. This may
be achieved by adding an adjustable voltage of up to ± 250 µV
at the unused input. (Pins 1 and 20 may be interchanged with
no change in function.)
In most applications there will be no need to use any offset
adjustment. However, a general offset trimming circuit is shown
in Figure 25. RS is the source resistance of the signal. Note: 50 Ω
rf sources may include a blocking capacitor and have no dc path to
ground, or may be transformer coupled and have a near zero resis-
tance to ground. Determine whether the source resistance is zero,
25 Ω or 50 Ω (with the generator terminated in 50 Ω) to find
the correct value of bias compensating resistor, RB, which
should optimally be equal to RS, unless RS = 0, in which case
use RB = 5 Ω. The value of ROS should be set to 20,000 RB to
provide a ± 250 µV trim range. To null the offset, set the source
voltage to zero and use a DVM to observe the logarithmic out-
put voltage. Recall that the LOG OUT current of the AD641
exhibits an absolute value response to the input voltage, so the
offset potentiometer is adjusted to the point where the logarithmic
output “turns around” (reaches a local maximum or minimum).
At high frequencies it may be desirable to insert a coupling
capacitor and use a choke between Pin 20 and ground, when
Pin 1 should be taken directly to ground. Alternatively, trans-
former coupling may be used. In these cases, there is no added
offset due to bias currents. When using two dc-coupled AD641s
(overall gain 100,000), it is impractical to maintain a sufficiently
low offset voltage using a manual nulling scheme. The section
CASCADED OPERATION explains how the offset can be
automatically nulled to submicrovolt levels by the use of a nega-
tive feedback network.
RS
(SOURCE
RESISTANCE
OF
TERMINATED
GENERATOR)
20 19
AD641
12
RB
+5V
20k⍀
ROS
–5V
Figure 25. Optional Input Offset Voltage Nulling Circuit;
See Text for Component Values
REV. C
–11–
11 Page | ||
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