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5962-9232501VXAのメーカーはNational Semiconductorです、この部品の機能は「3A/ 55V H-Bridge」です。 |
部品番号 | 5962-9232501VXA |
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部品説明 | 3A/ 55V H-Bridge | ||
メーカ | National Semiconductor | ||
ロゴ | |||
このページの下部にプレビューと5962-9232501VXAダウンロード(pdfファイル)リンクがあります。 Total 13 pages
December 1999
LMD18200
3A, 55V H-Bridge
General Description
The LMD18200 is a 3A H-Bridge designed for motion control
applications. The device is built using a multi-technology pro-
cess which combines bipolar and CMOS control circuitry
with DMOS power devices on the same monolithic structure.
Ideal for driving DC and stepper motors; the LMD18200 ac-
commodates peak output currents up to 6A. An innovative
circuit which facilitates low-loss sensing of the output current
has been implemented.
Features
n Delivers up to 3A continuous output
n Operates at supply voltages up to 55V
n Low RDS(ON) typically 0.3Ω per switch
n TTL and CMOS compatible inputs
n No “shoot-through” current
n Thermal warning flag output at 145˚C
n Thermal shutdown (outputs off) at 170˚C
n Internal clamp diodes
n Shorted load protection
n Internal charge pump with external bootstrap capability
Applications
n DC and stepper motor drives
n Position and velocity servomechanisms
n Factory automation robots
n Numerically controlled machinery
n Computer printers and plotters
Functional Diagram
FIGURE 1. Functional Block Diagram of LMD18200
DS010568-1
© 1999 National Semiconductor Corporation DS010568
www.national.com
1 Page Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Supply Voltage (VS, Pin 6)
Voltage at Pins 3, 4, 5, 8 and 9
Voltage at Bootstrap Pins
(Pins 1 and 11)
Peak Output Current (200 ms)
Continuous Output Current (Note 2)
Power Dissipation (Note 3)
60V
12V
VOUT +16V
6A
3A
25W
Power Dissipation (TA = 25˚C, Free Air)
Junction Temperature, TJ(max)
ESD Susceptibility (Note 4)
Storage Temperature, TSTG
Lead Temperature (Soldering, 10 sec.)
3W
150˚C
1500V
−40˚C to +150˚C
300˚C
Operating Ratings(Note 1)
Junction Temperature, TJ
VS Supply Voltage
−40˚C to +125˚C
+12V to +55V
Electrical Characteristics (Note 5)
The following specifications
temperature range, −40˚C ≤
apply
TJ ≤
+fo1r25V˚SC,=a4ll2oVt,heurnlleimssitsotahreerwfoirseTAsp=ecTiJfie=d.2B5˚oCld. face
limits
apply
over
the
entire
operating
Symbol
Parameter
Conditions
Typ Limit
Units
RDS(ON)
RDS(ON)
VCLAMP
VIL
Switch ON Resistance
Switch ON Resistance
Clamp Diode Forward Drop
Logic Low Input Voltage
Output Current = 3A (Note 6)
Output Current = 6A (Note 6)
Clamp Current = 3A (Note 6)
Pins 3, 4, 5
0.33
0.4/0.6
Ω (max)
0.33
0.4/0.6
Ω (max)
1.2 1.5 V (max)
−0.1 V (min)
0.8 V (max)
IIL Logic Low Input Current
VIH Logic High Input Voltage
VIN = −0.1V, Pins = 3, 4, 5
Pins 3, 4, 5
−10 µA (max)
2 V (min)
12 V (max)
IIH Logic High Input Current
Current Sense Output
VIN = 12V, Pins = 3, 4, 5
IOUT = 1A (Note 8)
10 µA (max)
377 325/300 µA (min)
425/450
µA (max)
Current Sense Linearity
Undervoltage Lockout
1A ≤ IOUT ≤ 3A (Note 7)
Outputs turn OFF
±6 ±9
%
9 V (min)
11 V (max)
TJW
VF(ON)
IF(OFF)
TJSD
IS
tDon
ton
Warning Flag Temperature
Flag Output Saturation Voltage
Flag Output Leakage
Shutdown Temperature
Quiescent Supply Current
Output Turn-On Delay Time
Output Turn-On Switching Time
tDoff Output Turn-Off Delay Times
toff Output Turn-Off Switching Times
tpw Minimum Input Pulse Width
tcpr Charge Pump Rise Time
Pin 9 ≤ 0.8V, IL = 2 mA
TJ = TJW, IL = 2 mA
VF = 12V
Outputs Turn OFF
All Logic Inputs Low
Sourcing Outputs, IOUT = 3A
Sinking Outputs, IOUT = 3A
Bootstrap Capacitor = 10 nF
Sourcing Outputs, IOUT = 3A
Sinking Outputs, IOUT = 3A
Sourcing Outputs, IOUT = 3A
Sinking Outputs, IOUT = 3A
Bootstrap Capacitor = 10 nF
Sourcing Outputs, IOUT = 3A
Sinking Outputs, IOUT = 3A
Pins 3, 4 and 5
No Bootstrap Capacitor
145 ˚C
0.15 V
0.2 10 µA (max)
170 ˚C
13 25 mA (max)
300 ns
300 ns
100 ns
80 ns
200 ns
200 ns
75 ns
70 ns
1 µs
20 µs
3 www.national.com
3Pages Pinout Description
(See Connection Diagram) (Continued)
Pin 6, VS Power Supply
Pin 7, GROUND Connection: This pin is the ground return,
and is internally connected to the mounting tab.
Pin 8, CURRENT SENSE Output: This pin provides the
sourcing current sensing output signal, which is typically
377 µA/A.
Pin 9, THERMAL FLAG Output: This pin provides the ther-
mal warning flag output signal. Pin 9 becomes active-low at
145˚C (junction temperature). However the chip will not shut
itself down until 170˚C is reached at the junction.
Pin 10, OUTPUT 2: Half H-bridge number 2 output.
Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for
Half H-bridge number 2. The recommended capacitor
(10 nF) is connected between pins 10 and 11.
PWM
H
H
L
H
H
L
TABLE 1. Logic Truth Table
Dir Brake Active Output Drivers
H L Source 1, Sink 2
L L Sink 1, Source 2
X L Source 1, Source 2
H H Source 1, Source 2
L H Sink 1, Sink 2
X H NONE
Application Information
TYPES OF PWM SIGNALS
The LMD18200 readily interfaces with different forms of
PWM signals. Use of the part with two of the more popular
forms of PWM is described in the following paragraphs.
Simple, locked anti-phase PWM consists of a single, vari-
able duty-cycle signal in which is encoded both direction and
amplitude information (see Figure 2). A 50% duty-cycle
PWM signal represents zero drive, since the net value of
voltage (integrated over one period) delivered to the load is
zero. For the LMD18200, the PWM signal drives the direc-
tion input (pin 3) and the PWM input (pin 5) is tied to logic
high.
DS010568-4
FIGURE 2. Locked Anti-Phase PWM Control
Sign/magnitude PWM consists of separate direction (sign)
and amplitude (magnitude) signals (see Figure 3). The (ab-
solute) magnitude signal is duty-cycle modulated, and the
absence of a pulse signal (a continuous logic low level) rep-
resents zero drive. Current delivered to the load is propor-
tional to pulse width. For the LMD18200, the DIRECTION in-
put (pin 3) is driven by the sign signal and the PWM input
(pin 5) is driven by the magnitude signal.
DS010568-5
FIGURE 3. Sign/Magnitude PWM Control
SIGNAL TRANSITION REQUIREMENTS
To ensure proper internal logic performance, it is good prac-
tice to avoid aligning the falling and rising edges of input sig-
nals. A delay of at least 1 µsec should be incorporated be-
tween transitions of the Direction, Brake, and/or PWM input
signals. A conservative approach is be sure there is at least
500ns delay between the end of the first transition and the
beginning of the second transition. See Figure 4.
www.national.com
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部品番号 | 部品説明 | メーカ |
5962-9232501VXA | 3A/ 55V H-Bridge | National Semiconductor |