FOD2200SDV Datasheet PDF - Fairchild Semiconductor
| Part Number | FOD2200SDV | |
| Description | LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS | |
| Manufacturers | Fairchild Semiconductor | |
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There is a preview and FOD2200SDV download ( pdf file ) link at the bottom of this page. Total 14 Pages | ||
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LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
DESCRIPTION
The FOD2200 is an optically coupled logic gate that combine an AlGaAs LED
and an integrated high gain photo detector. The detector has a three state
output stage and has a detector threshold with hysteresis. The three state
output eliminates the need for a pullup resistor and allows for direct drive of
data busses. The hysteresis provides differential mode noise immunity and
eliminates the potential for output signal chatter.
The Electrical and Switching Characteristics of the FOD2200 are guaranteed
over the temperature range of 0°C to 85°C and a VCC range of 4.5 volts to 20
volts. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and
CMOS logic and result in lower power consumption compared to other high
speed optocouplers. Logic signals are transmitted with a maximum propaga-
tion delay of 300 nsec. The FOD2200 is useful for isolating high speed logic
interfaces, buffering of input and output lines, and implementing isolated line
receivers in high noise environments.
8
1
8
1
8
1
FEATURES
• 1 kV/µs Minimum Common Mode
Rejection
• Compatible with LSTTL, TTL, and CMOS
Logic
• Wide VCC Range (4.5 to 20 V)
• 2.5 Mbd Guaranteed over Temperature
• Low Input Current (1.6 mA)
• Three State Output (No Pullup Resistor
Required)
• Guaranteed Performance from 0°C to 85°C
• Hysteresis
• Safety Approvals Pending – UL, CSA, VDE
• VISO = 5kVRMS
APPLICATION
• Isolation of High Speed Logic Systems
• Computer-Peripheral Interfaces
• Microprocessor System Interfaces
• Ground Loop Elimination
• Pulse Transformer Replacement
• Isolated Buss Driver
• High Speed Line Receiver
NC 1
ANODE 2
CATHODE 3
NC 4
Schematic
IF
+
2
VF
–
3
SHIELD
SHIELD
8 VCC
7 VO
6 VE
5 GND
ICC
VCC
8
IO
7 VO
IE
6 VE
GND
5
TRUTH TABLE (Positive Logic)
LED
On
Off
On
Off
Enable
H
H
L
L
© 2004 Fairchild Semiconductor Corporation
Page 1 of 14
Output
Z
Z
H
L
7/7/04
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LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
NOTES
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC
and GND pins of each device.
2. tPLH - Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse to the
1.3V level on the LOW to HIGH transition of the output voltage pulse.
3. tPHL - Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse to the 1.3V
level on the HIGH to LOW transition of the output voltage pulse.
4. When the peaking capacitor is omitted, propagation delay times may increase by 100 ns.
5. tr - Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
6. tf - Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
7. CMH - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e.,
VOUT > 2.0 V).
8. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e.,
VOUT < 0.8 V).
9. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
10. Duration of output short circuit time should not exceed 10 ms.
© 2004 Fairchild Semiconductor Corporation
Page 5 of 14
7/7/04
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FOD2200SDV electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FOD2200SDV.PDF Datasheet ] | |
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