PDF DS92LV1210TMSA Data sheet ( Hoja de datos )

Número de pieza	DS92LV1210TMSA
Descripción	16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
Fabricantes	National Semiconductor
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No Preview Available ! March 1999 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1021 transforms a 10-bit wide parallel CMOS/ TTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1210 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and separates clock. The DS92LV1021 may transmit data over heavily loaded back- planes or 10 meters of cable. The reduced cable, PCB trace count and connector size saves cost and makes PCB design layout easier. Clock-to-data and data-to-data skew are elimi- nated since one output will transmit both clock and all data bits serially. The powerdown pin is used to save power, by reducing supply current when either device is not in use. The Serializer has a synchronization mode that should be acti- vated upon power-up of the device. The Deserializer will es- tablish lock to this signal within 1024 cycles, and will flag Lock status. The embedded clock guarantees a transition on the bus every 12-bit cycle; eliminating transmission errors due to charged cable conditions. The DS92LV1021 output pins may be TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz. Features n Guaranteed transition every data transfer cycle n Single differential pair eliminates multi-channel skew n Flow-through pinout for easy PCB layout n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits n Synchronization mode and LOCK indicator n Programmable edge trigger on clock n High impedance on receiver inputs when power is off n Bus LVDS serial output rated for 27Ω load n Small 28-lead SSOP package-MSA Block Diagrams TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100110 DS100110-1 www.national.com 1 page Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) IIN Input Current VIN = +2.4V, VCC = 3.6V or 0V VIN = 0V, VCC = 3.6V or 0V SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) ICCD Serializer Supply Current Worst Case RL = 27Ω Figure 1 f = 40 MHz f = 16 MHz ICCXD Serializer Supply Current Powerdown PWRDN = 0.8V DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) ICCR Deserializer Supply Current Worst Case CL = 15 pF Figure 2 f = 40 MHz f = 16 MHz ICCXR Deserializer Supply Current PWRDN = 0.8V, REN = 0.8V Powerdown Min Typ Max Units −10 ±1 +10 µA −15 ±1 +15 µA 32 55 mA 25 45 mA 4 10 mA 44 75 mA 31 55 mA 1.5 5.0 mA Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ tTCP tTCIH tTCIL tCLKT tJIT Transmit Clock Period Transmit Clock High Time Transmit Clock Low Time TCLK Input Transition Time TCLK Input Jitter 25 0.4T 0.4T T 0.5T 0.5T 3 Max 62.5 0.6T 0.6T 6 150 Units ns ns ns ns ps Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ tLLHT tLHLT Bus LVDS Low-to-High Transition Time Bus LVDS High-to-Low Transition Time RL = 27Ω Figure 3 CL=10pF to GND 0.2 0.25 tDIS DIN (0-9) Setup to TCLK Figure 6 tDIH DIN (0-9) Hold from TCLK RL = 27Ω, CL=10pF to GND tHZD DO ± HIGH to Figure 7 (Note 4) TRI-STATE Delay RL = 27Ω, tLZD DO ± LOW to TRI-STATE CL=10pF to GND Delay tZHD DO ± TRI-STATE to HIGH Delay 1.0 6.5 0 4.5 3.5 2.9 2.5 tZLD DO ± TRI-STATE to LOW Delay 2.7 tSPW tPLD tSD tBIT SYNC Pulse Width Serializer PLL Lock Time Serializer Delay Bus LVDS Bit Width Figure 8 RL = 27Ω Figure 9 RL = 27Ω RL = 27Ω, CL=10pF to GND 1024tTCP 2048tTCP tTCP tTCP + 2.5 tCLK / 12 Max 1 1 10 10 10 10 1029tTCP 2049tTCP tTCP+ 5 Units ns ns ns ns ns ns ns ns ns ns ns ns 5 www.national.com 5 Page AC Timing Diagrams and Test Circuits (Continued) FIGURE 14. Deserializer PLL Lock Time from SyncPAT DS100110-22 DS100110-21 SW - Setup and Hold Time (Internal data sampling window) tJIT- Serializer Output Bit Position Jitter tRSM = Receiver Sampling Margin Time FIGURE 15. Receiver Bus LVDS Input Skew Margin VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. DS100110-16 11 www.national.com 11 Page

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Número de pieza	Descripción	Fabricantes
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