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PDF DS90CF561 Data sheet ( Hoja de datos )
| Número de pieza | DS90CF561 | |
| Descripción | LVDS 18-Bit Color Flat Panel Display (FPD) Link | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1997
DS90CF561/DS90CF562
LVDS 18-Bit Color Flat Panel Display (FPD) Link
General Description
The DS90CF561 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF562 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE, FP-
FRAME, DRDY) are transmitted at a rate of 280 Mbps per
LVDS data channel. Using a 40 MHz clock, the data through-
put is 105 Megabytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n Up to 105 Megabyte/sec bandwidth
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design
n Power down mode
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Falling edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CF561
DS90CF562
Order Number DS90CF561MTD
See NS Package Number MTD48
DS012485-26
Order Number DS90CF562MTD
See NS Package Number MTD48
DS012485-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012485
www.national.com
1 page  
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCCD
TPLLS
TPDD
Parameter
TxCLK IN to TxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 9)
Transmitter Phase Lock Loop Set (Figure 11)
Transmitter Powerdown Delay (Figure 15)
Note 5: This limit based on bench characterization.
Min Typ Max Units
5 9.7 ns
10 ms
100 ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RCOP
RSKM
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4)
CMOS/TTL High-to-Low Transition Time (Figure 4)
RxCLK OUT Period (Figure 8)
Receiver Skew Margin (Note 6). VCC = 5V, TA = 25˚C (Figure 18)
RCOH RxCLK OUT High Time (Figure 8)
RCOL RxCLK OUT Low Time (Figure 8)
RSRC RxOUT Setup to RxCLK OUT (Figure 8)
RHRC RxOUT Hold to RxCLK OUT (Figure 8)
RCCD
RPLLS
RPDD
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 10)
Receiver Phase Lock Loop Set (Figure 12)
Receiver Powerdown Delay (Figure 16)
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
Min Typ
3.5
2.7
25 T
1.1
700
21.5
10.5
19
6
14
4.5
16
6.5
7.6
Max Units
6.5 ns
6.5 ns
50 ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
11.9 ns
10 ms
1 µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew(TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock(TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
5
DS012485-5
www.national.com
5 Page 
DS90CF561 Pin Description — FPD Link Transmitter
Pin Name I/O No.
Description
TxIN
I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME,
DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
TxOUT+
O 3 Positive LVDS differential data output
TxOUT−
O 3 Negative LVDS differential data output
FPSHIFT IN
I 1 TTL level clock input. The falling edge acts as data strobe.
TxCLK OUT+ O 1 Positive LVDS differential clock output
TxCLK OUT− O 1 Negative LVDS differential clock output
PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
VCC
GND
I 4 Power supply pins for TTL inputs
I 5 Ground pins for TTL inputs
PLL VCC
PLL GND
I 1 Power supply pin for PLL
I 2 Ground pins for PLL
LVDS VCC
LVDS GND
I 1 Power supply pin for LVDS outputs
I 3 Ground pins for LVDS outputs
DS90CF562 Pin Description — FPD Link Receiver
Pin Name I/O No.
Description
RxIN+
I 3 Positive LVDS differential data inputs
RxIN−
I 3 Negative LVDS differential data inputs
RxOUT
O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
RxCLK IN+
I 1 Positive LVDS differential clock input
RxCLK IN−
I 1 Negative LVDS differential clock input
FPSHIFT OUT O 1 TTL level clock output. The falling edge acts as data strobe.
PWR DOWN I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
VCC
GND
I 4 Power supply pins for TTL outputs
I 5 Ground pins for TTL outputs
PLL VCC
PLL GND
I 1 Power supply for PLL
I 2 Ground pin for PLL
LVDS VCC
LVDS GND
I 1 Power supply pin for LVDS inputs
I 3 Ground pins for LVDS inputs
11 www.national.com
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| PDF Descargar | [ Datasheet DS90CF561.PDF ] | |
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