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PDF ETL9444 Data sheet ( Hoja de datos )
| Número de pieza | ETL9444 | |
| Descripción | 4-BIT NMOS MICROCONTROLLERS | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ETL9444/ETL9445
ETL9344/ETL9345
4-BIT NMOS MICROCONTROLLERS
. LOW COST
. POWERFUL INSTRUCTION SET
. 2k x 8 ROM, 128 x 4 RAM
. 23 I/O LINES (ETL9444)
. TRUE VECTORED INTERRUPT, PLUS RES-
TART
. THREE-LEVEL SUBROUTINE STACK
. 16µs INSTRUCTION TIME
. SINGLE SUPPLY OPERATION (4.5-6.3V)
. LOW CURRENT DRAIN (13mA max.)
. INTERNAL TIME-BASE COUNTER FOR REAL-
TIME PROCESSING
. INTERNAL BINARY COUNTER REGISTER
WITH MICROWIRE® SERIAL I/O CAPABILITY
. GENERAL PURPOSE AND TRI-STATE® OUT-
PUTS
. LSTTL/CMOS COMPATIBLE IN AND OUT
. DIRECT DRIVE OF LED DIGIT AND SEGMENT
LINES
. SOFTWARE/HARDWARE
COMPATIBLE
WITH OTHER MEMBERS OF ET9400 FAMILY
. EXTENDED TEMPERATURE RANGE DE-
VICES
ETL9344/L9345 (– 40°C to + 85°C)
. WIDER SUPPLY RANGE (4.5 – 9.5V)
OPTIONALLY AVAILABLE
. SOIC 24/28 AND PLCC 28 PACKAGES AVAI-
LABLE
ETL9444/ETL9344
N
(Plastic Package)
ETL9345/ETL9345
N
(Plastic Package)
PIN CONNECTION
D E SC RI PT I O N
The ETL9444/L9445 and ETL9344/L9345 Single-
Chip N-Channel Microcontrollers are fully compati-
ble with the COPS® family, fabricated using
N-channel, silicon gate XMOS technology. They are
complete microcomputers containing all system ti-
ming, internal logic, ROM, RAM and I/O necessary
to implement dedicated control functions in a variety
of applications. Features include single supply ope-
ration, a variety of output configuration options, with
an instruction set, internal architecture and I/O
scheme designed to facilitate keyboard input, dis-
play output and BCD data manipulation. The
ETL9445 is identical to the ETL9444, except with 19
I/O lines instead of 23 : They are an appropriate
choice for use in numerous human interface control
environments. Standard test procedures and relia-
ble high-density fabrication techniques provide the
medium to large volume customers with a customi-
May 1989
1/27
1 page  
ET L9 44 4/ 94 4 5 –ET L 9 344 / 9 3 45
ETL9344/L9345
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
Voltage at any Pin Relative to GND
– 0.5 to + 10
V
Ambient Operating Temperature
– 40 to + 85
°C
Ambient Storage Temperature
– 65 to + 150
°C
Lead Temperature (soldering, 10 seconds)
300 °C
Power Dissipation
0.75W at 25°C
0.25W at 85°C
Total Source Current
120 mA
Total Sink Current
120 mA
Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not en-
sured when operating the device at absolute maximum ratings.
DC ELECTRICAL CHARACTERISTICS – 40°C ≤ TA ≤ + 85°C, 4.5V ≤ VCC ≤ 7.5V
(unless otherwise specified)
Parameter
Test Conditions
Min.
Standard Operating Voltage (V CC)
Optional Operating Voltage (V CC)
Power Supply Ripple
Operating Supply Current
Note 1
Peak to Peak
All Inputs and Outputs Open
4.5
4.5
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (V IH)
Logic Low (V IL )
Schmitt Trigger Input
Logic High (V IH)
Logic Low (V IL )
RESET Input Levels
Logic High
Logic Low
SO Input Level (test mode)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
Input Capacitance
Hi-Z Input Leakage
Schmitt Trigger Input
VCC = Max.
With TTL trip level options
selected, VCC = 5V ± 5%
With high trip level options
selected
2.2
– 0.3
0.7 VCC
– 0.3
0.7 VCC
– 0.3
2.2
3.0
2.2
– 0.3
3.6
– 0.3
–2
Output Voltage Levels
LSTTL Operation
Logic High (V OH)
Logic Low (V OL )
CMOS Operation
Logic High
Logic Low
VCC = 5V ± 5%
I OH = – 20µA
I OL = 0.36mA
I OH = – 10µA
I OL = + 10µA
2.7
VCC – 1
Note : 1. VCC voltage change must be less than 0.5V in a 1ms period to maintain proper operation.
Max.
5.5
7.5
0.5
15
0.3
0.4
0.4
2.5
0.6
1.2
7
+2
0.4
0.2
Unit
V
V
V
mA
V
V
V
V
V
V
V
V
V
V
V
V
pF
µA
V
V
V
V
5/27
5 Page 
ET L9 44 4/ 94 4 5 –ET L 9 344 / 9 3 45
4. All successive transfer of control instructions
and successive LBIs have been completed
(e.g., if the main program is executing a JP in-
struction which transfers program control to
another JP instruction, the interrupt will not be
acknowledged until the second JP instruction
has been executed.
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon pop-
ping of the stack. For example, if an interrupt oc-
curs during the execution of ASC (Add with
Carry, Skip on Carry) instruction which results in
carry, the skip logic status is saved and program
control is transferred to the interrupt servicing
routine at hex address 0FF. At the end of the in-
terrupt routine, a RET instruction is executed to
”pop” the stack and return program control to the
instruction following the original ASC. At this
time, the skip logic is enabled and skips this in-
struction because of the previous ASC carry.
Subroutines and LQIDinstructions should not be
nested within the interrupt service routine, since
their popping the stack will enable any previously
saved main program skips, interfering with the
orderly execution of the interrupt routine.
d. The first instruction of the interrupt routine at hex
address 0FF must be a NOP.
e. A LEI instruction can be put immediately before
the RET to re-enable interrupts.
INITIALIZATION
The Reset Logic will initialize (clear) the device upon
power-up if the power supply rise time is less than
1ms and greater than 1µs. If the power supply rise
time is greater than 1ms, the user use provide an ex-
ternal RC network and diode to the RESET pin as
shown below. If the RC network is not used, the RE-
SET pin must be pulled up to VCC either by the in-
ternal load or by an external resistor (≥40kΩ) to VCC.
The RESET pin is configured as a Schmitt trigger in-
put. Initialization will occur whenever a logic ”0” is
applied to the RESET input, provided it stays low for
at least three instruction cycle times.
Power-up Clear Circuit.
Upon initialization, the PC register is cleared to 0
(ROM address 0) and the A, B, C, D, EN, and G re-
gisters are cleared. The SK output is enabled as a
SYNC output, providing a pulse each instruction cy-
cle time. Data Memory (RAM) is not cleared upon i-
nitialization. The first instruction at address 0 must
be a CLRA.
OSCILLATOR
There are three basic clock oscillator configurations
available as shown by figure 4.
a. Crystal Controlled Oscillator. CKI and CKO
are connected to an external crystal. The instruc-
tion cycle time equals the crystal frequency divi-
ded by 32 (optional by 16 or 8).
b. External Oscillator. CKI is an external clock in-
put signal. The external frequency is divided by
32 (optional by 16 or 8) to give the instruction cy-
cle time. CKO is now available to be used as the
RAM power supply (VR), as a general purpose
input, or as a SYNC input.
c. RC Controlled Oscillator. CKI is configured as
a single pin RC controlled Schmitt trigger oscil-
lator. The instruction cycle equals the oscillation
frequency divided by 4. CKO is available as the
RAM power supply (VR) or as a general purpose
input.
11/27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ETL9444.PDF ] | |
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