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ETC5067FN の電気的特性と機能

ETC5067FNのメーカーはSTMicroelectronicsです、この部品の機能は「POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE」です。


製品の詳細 ( Datasheet PDF )

部品番号 ETC5067FN
部品説明 POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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ETC5067FN Datasheet, ETC5067FN PDF,ピン配置, 機能
ETC5064/64-X
ETC5067/67-X
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE
POWER AMPLIFIER
. COMPLETE CODEC AND FILTERING SYS-
TEM INCLUDING :
- Transmit high-pass and low-pass filtering.
- Receive low-pass filter with sin x/x correction.
- Active RC noise filter.
- µ-law or A-law compatible CODER and DE-
CODER.
- Internal precision voltage reference.
- Serial I/O interface.
- Internal auto-zero circuitry.
- Receive push-pull power amplifiers.
. µ-LAW ETC5064
. A-LAW ETC5067
. MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.
. ± 5 V OPERATION.
. LOW OPERATING POWER-TYPICALLY 70 mW
. POWER-DOWN STANDBY MODE-TYPICALLY
3 mW
. AUTOMATIC POWER DOWN
. TTL OR CMOS COMPATIBLE DIGITAL INTER-
FACES
. MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
. 0°C TO 70°C OPERATION: ETC5064/67
. –40°C TO 85°C OPERATION: ETC5064-X/67-X
DIP20
(Plastic) N
ORDERING NUMBERS:
ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X
PL CC2 0
FN
DESCRIPTION
The ETC5064 (µ-law), ETC5067 (A-law) are mono-
lithic PCM CODEC/FILTERS utilizing the A/D and
D/A conversion architectureshown in the Block Dia-
grams and a serial PCM interface. The devices are
fabricated using double-poly CMOS process.
Similar to the ETC505X family, these devices fea-
ture an additional Receive Power Amplifier to pro-
vide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two ex-
ternal resistors for an output level of up to ± 6.6 V
across a balanced 600load.
Also included is an Analog Loopback switch and
TSX output.
ORDERING NUMBERS:
ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
SO 20
D
ORDERING NUMBERS:
ETC5064D
ETC5064D-X
ETC5067D
ETC5067D-X
November 1994
1/18

1 Page





ETC5067FN pdf, ピン配列
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN DESCRIPTION
Name
VPO+
GNDA
VPO-
VPI
Pi n
Type (*)
O
GND
O
I
VFRO
VCC
FSR
O
S
I
DR I
BCLKR/CLKSEL
I
MCKLR/PDN
I
MCLKX
BCLKX
DX
FSX
TSX
ANLB
GSX
VFXI-
VFXI+
VBB
I
I
O
I
O
I
O
I
I
S
N Description
1 The Non-inverting Output of the Receive Power Amplifier
2 Analog Ground. All signals are referenced to this pin.
3 The Inverting Output of the Receive Power Amplifier
4 Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to VBB.
5 Analog Output of the Receive Filter.
6 Positive Power Supply Pin. VCC = +5V ±5%
7 Receive Frame Sync Pulse which enable BCLKR to shift PCM data into
DR. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.
8 Receive Data Input. PCM data is shifted into DR following the FSR leading
edge
9 The bit Clock which shifts data into DR after the FSR leading edge. May
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLKX is used
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
10 Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKX, but should be synchronous with MCLKX for
best performance. When MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
11 Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKR.
12 The bit clock which shifts out the PCM data on DX. May vary from 64KHz
to 2.048MHz, but must be synchronous with MCLKX.
13 The TRI-STAT E®PCM data output which is enabled by FSX.
14 Transmit frame sync pulse input which enables BCLKX to shift out the
PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for
timing details.
15 Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
16 Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO+
output of the receive power amplifier.
17 Analog output of the transmit input amplifier. Used to set gain externally.
18 Inverting input of the transmit input amplifier.
19 Non-inverting input of the transmit input amplifier.
20 Negative Power Supply Pin. VBB = -5V ±5%
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE® is a trademark of National Semiconductor Corp.
3/18


3Pages


ETC5067FN 電子部品, 半導体
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS
VCC = 5.0V ±5%, VBB = -5V ±5%, GNDA = 0V, TA = 0°C to70°C (ETC5064-X/67-X: TA = –40°C to 85°), unless
otherwise noted; typical characteristics specified at VCC = 5.0V, VBB =-5.0V, TA = 25°C; all signals are refer-
enced to GNDA.
DIGITAL INTERFACE (All devices)
Symbol
Parameter
Min.
VIL Input Low Voltage
VIH Input High Voltage
2.2
VOL Output Low Voltage
IL = 3.2 mA
IL = 3.2 mA, Open Drain
DX
TSX
VOH Output High Voltage
IH = 3.2 mA
DX 2.4
IIL Input Low Current (GNDA VIN VIL )all digital inputs
Except BCLKR
– 10
IIH Input High Current (VIH VIN VCC) Except ANLB
– 10
IOZ Output Current in High Impedance State (TRI-STAT E)
(GNDA VO VCC)
DX – 10
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Typ.
Max.
0.6
0.4
0.4
10
10
10
Unit
V
V
V
V
V
µA
µA
µA
Symbol
IIXA
RIXA
ROXA
RLXA
CLXA
VOXA
AVXA
FUXA
VOSXA
VCMXA
CMRRXA
PSRRXA
Parameter
Input Leakage Current
(– 2.5 V V + 2.5 V)
Input Resistance
(– 2.5 V V + 2.5 V)
Output Resistance (closed loop, unity gain)
Load Resistance
Load Capacitance
Output Dynamic Range (RL 10 k)
Voltage Gain (VFXI + to GSX)
Unity Gain Bandwidth
Offset Voltage
Common-mode Voltage
Common-mode Rejection Ratio
Power Supply Rejection Ratio
VFxI + or VFxI
VFXI + or VFXI
GSX
GSX
GSX
Min. Typ.
– 200
10
1
10
– 2.8
5000
1
– 20
– 2.5
60
60
2
Max.
200
3
50
+2.8
20
2.5
Unit
nA
M
k
pF
V
V/V
MHz
mV
V
dB
dB
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol
RORF
RLRF
CLRF
VOSRO
Parameter
Output Resistance
Load Resistance (VFRO = ± 2.5 V)
Load Capacitance
Output DC Offset Voltage
VFRO
Min.
10
Typ.
1
– 200
Max.
3
25
200
Unit
k
pF
mV
6/18

6 Page



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共有リンク

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部品番号部品説明メーカ
ETC5067FN

POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE

STMicroelectronics
STMicroelectronics
ETC5067FN-X

POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE

STMicroelectronics
STMicroelectronics


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