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PDF ETC5057D Data sheet ( Hoja de datos )
| Número de pieza | ETC5057D | |
| Descripción | SERIAL INTERFACE CODEC/FILTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ETC5054
® ETC5057
SERIAL INTERFACE CODEC/FILTER
COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
– µ-law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
A-LAW 16 PINS (ETC5057FN, 20 PINS)
µ-LAW WITHOUT SIGNALING, 16 PINS
(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS
±5V OPERATION
LOW OPERATING POWER - TYPICALLY 60
mW
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70°C OPERATION
DIP16 (Plastic)
ORDERING NUMBERS:
ETC5057N
ETC5054N
SO16 (Wide)
ORDERING NUMBERS:
ETC5057D
ETC5054D
DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and µ–law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or µ–law PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or µ–law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
PLCC20
ORDERING NUMBERS:
ETC5057FN
ETC5054FN
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
March 2000
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1 page  
ETC5054 - ETC5057
edges clock out the remaining seven bits. The DX
output is disabled by the falling BCLKX edge fol-
lowing the eighth rising edge, or by FSX going
low, which-ever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKX in synchronous
mode). Both devices may utilize the long frame
sync pulse in synchronous or asynchronous
mode.
TRANSMIT SECTION
The transmit section input is an operational ampli-
fier with provision for gain adjustment using two
external resistors, see figure 6. The low noise and
wide bandwidth allow gains in excess of 20 dB
across the audio passband to be realized. The op
amp drives a unitygain filter consisting of RD ac-
tive pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 256
kHz. The output of this filter directly drives the en-
coder sample-and-hold circuit. The A/D is of com-
panding type according to A-law (ETC5057) or µ–
law (ETC5054) coding conventions. A precision
voltage reference is trimmed in manufacturing to
provide an input overload (tMAX) of nominally 2.5V
peak (see table of transmission characteristics).
The FSX frame sync pulse controls the sampling
of the filter output, and then the successive-ap-
proximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through DX at the next FSX pulse. The total en-
coding delay will be approximately 165 µs (due to
the transmit filter) plus 125µs (due to encoding
delay), which totals 290µs. Any offset vol-tage
due to the filters or comparator is cancelled by
sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding
DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is
A-law (ETC5057) or µ–law (ETC5054) and the
5th order low pass filter corrects for the sin x/x at-
tenuation due to the 8 kHz sample and hold.
The filter is then followed by a 2nd order RC ac-
tive post-filter and power amplifier capable of driv-
ing a 600Ω load to a level of 7.2 dBm. The re-
ceive section is unity-gain. Upon the occurence of
FSR, the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) pe-
riods. At the end of the decoder time slot, the de-
coding cycle begins, and 10µs later the decoder
DAC output is updated. The total decoder delay
is ∼ 10µs (decoder update) plus 110µs (filter
delay) plus 62.5µs (1/2 frame), which gives ap-
proximately 180µs. A mute circuitry is a active
during 10ms when power up.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VBB
VIN, VOUT
Toper
Tstg
Parameter
VCC to GNDA
VBB to GNDA
Voltage at any Analog Input or Output
Voltage at Any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Value
7
–7
VCC + 0.3 to VBB – 0.3
VCC + 0.3 to GNDA – 0.3
– 25 to + 125
– 65 to + 150
300
Unit
V
V
V
V
°C
°C
°C
ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V ± 5 %, VBB = – 5.0 V ± 5%GNDA = 0 V,
TA = 0 °C to 70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA = 25 °C ; all signals
are referenced to GNDA.
Symbol
VIL
VIH
VOL
VOH
IIL
IIH
IOZ
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
IL = 3.2mA
IL = 3.2mA, Open Drain
Output High Voltage
IH = 3.2mA
Input Low Current (GNDA ≤ VIN ≤ VIL, all digital inputs)
Input High Current (VIH ≤ VIN ≤ VCC) except BCLKR/BCLKSEL
Output Current in HIGH Impedance State (TRI-STATE)
(GNDA ≤ VO ≤ VCC)
DX
TSX
DX
DX
Min.
2.2
2.4
–10
–10
–10
Typ.
Max.
0.6
0.4
0.4
10
10
10
Unit
V
V
V
V
V
µA
µA
µA
5/18
5 Page 
TRANSMISSION (continued)
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol
Parameter
DXA Transmit Delay, Absolute (f = 1600Hz)
DXR Transmit Delay, Relative to DXA
f = 500Hz - 600Hz
f = 600Hz - 800Hz
f = 800Hz - 1000Hz
f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz
DRA Receive Delay, Absolute (f = 1600Hz)
DRR Receive Delay, Relative to DRA
f = 500Hz - 1000Hz
f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz
ETC5054 - ETC5057
Min.
– 40
– 30
Typ.
290
195
120
50
20
55
80
130
180
– 25
– 20
70
100
145
Max.
315
220
145
75
40
75
105
155
200
90
125
175
Unit
µs
µs
µs
µs
NOISE
Symbol
NXP
NRP
NXC
NRC
NRS
PPSRX
NPSRX
PPSRR
NPSRR
Parameter
Transmit Noise, P Message Weighted (A LAW, VFXI + = 0 V)
1)
Receive Noise, P Message Weighted
(A LAW, PCM code equals positive zero)
Transmit Noise, C Message Weighted µ LAW (VFXI + = 0 V)
Receive Noise, C Message Weighted
(µ LAW, PCM Code Equals Alternating Positive and Negative Zero)
Noise, Single Frequency
f = 0 kHz to 100 kHz, Loop around Measurement,
VFXI + = 0 Vrms
Positive Power Supply Rejection, Transmit (note 2)
VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
Negative Power Supply Rejection, Transmit (note 2)
VBB = – 5.0 VDC + 100 mVrms,
f = 0 kHz-50 kHz
Positive Power Supply Rejection, Receive
(PCM code equals positive zero, VCC = 5.0 VDC + 100mVrms)
f = 0Hz to 4000Hz
f = 4KHz to 25KHz
f = 25KHz to 50KHz
Negative Power Supply Rejection, Receive
(PCM code equals positive zero, VBB = 5.0 VDC + 100mVrms)
f = 0Hz to 4000Hz
f = 4KHz to 25KHz
f = 25KHz to 50KHz
Min.
40
40
40
40
36
40
40
36
Typ.
– 74
– 82
12
8
Max. Unit
– 69 dBm0p
– 79 dBm0p
15 dBmC0
11 dBrnC0
– 53 dBm0
dBp
dBp
dBp
dB
dB
dBp
dB
dB
11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ETC5057D.PDF ] | |
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