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ETC5054N の電気的特性と機能

ETC5054NのメーカーはSTMicroelectronicsです、この部品の機能は「SERIAL INTERFACE CODEC/FILTER」です。


製品の詳細 ( Datasheet PDF )

部品番号 ETC5054N
部品説明 SERIAL INTERFACE CODEC/FILTER
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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ETC5054N Datasheet, ETC5054N PDF,ピン配置, 機能
ETC5054
® ETC5057
SERIAL INTERFACE CODEC/FILTER
COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
µ-law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
A-LAW 16 PINS (ETC5057FN, 20 PINS)
µ-LAW WITHOUT SIGNALING, 16 PINS
(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS
±5V OPERATION
LOW OPERATING POWER - TYPICALLY 60
mW
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70°C OPERATION
DIP16 (Plastic)
ORDERING NUMBERS:
ETC5057N
ETC5054N
SO16 (Wide)
ORDERING NUMBERS:
ETC5057D
ETC5054D
DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and µ–law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or µ–law PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or µ–law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
PLCC20
ORDERING NUMBERS:
ETC5057FN
ETC5054FN
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
March 2000
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1 Page





ETC5054N pdf, ピン配列
ETC5054 - ETC5057
PIN DESCRIPTION
Name
VBB
GNDA
VFRO
VCC
FSR
Pin
Type
*
S
GND
O
S
I
DR I
BCLKR/CLKSEL I
MCLKR/PDN
I
MCLKX
BCLKX
DX
FSX
TSX
GSX
VFXI
VFXI+
I
I
O
I
O
O
I
I
N° N°
DIP PLCC
and
SO (**)
11
22
33
45
56
67
78
Fun ction
Negative
Power Supply
Analog Ground
Receive Filter
Output
Positive Power
Supply
Receive Frame
Sync Pulse
Receive Data
Input
Shift-in Clock
8 9 Receive Master Clock
9 12 Transmit Master Clock
10 14
Shift-out Clock
11 15
12 16
Transmit
Data Output
Transmit Frame
Sync Pulse
13 17 Transmit Time Slot
14 18
Gain Set
15 19
Inverting Amplifier
Input
16 20 Non-inverting Amplifier
Input
Description
VBB = – 5 V ± 5 %.
All signals are referenced to this pin.
Analog Output of the Receive Filter
VCC = + 5 V ± 5 %.
Enables BCLKR to shift PCM data into DR. FSR is an
8kHz pulse train. See figures 1, 2 and 3 for timing
details.
PCM data is shifted into DR following the FSR leading
edge.
Shifts data into DR after the FSR leading edge. May
vary from 64 kHz to 2.048 MHz. Alternatively, may be
a logic input which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in synchronous
mode and BCLKX is used for both transmit and receive
directions (see table 1). This input has an internal pull-
up.
Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKX, but should be
synchronous with MCLKX for best performance. When
MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is
connected continuously high, the device is powered
down.
Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKR.
Shifts out the PCM data on DX. May vary from 64 kHz
to 2.048 MHz, but must be synchronous with MCLKX.
The TRI-STATE® PCM data output which is enabled
by FSX.
Enables BCLKX to shift out the PCM data on DX. FSX is
an 8 kHz pulse train. See figures 1, 2 and 3 for timing
details.
Open drain output which pulses low during the encoder
time slot. Recommended to be grounded if not used.
Analog output of the transmit input amplifier. Used to
set gain externally.
Inverting Input of the Transmit Input Amplifier.
Non-inverting Input of the Transmit Input Amplifier.
(*) I: Input, O: Output, S: Power Supply
(**) Pins 4,10,11 and 13 are not connected
TRI-STATE ®is a trademark of National Semiconductor Corp.
3/18


3Pages


ETC5054N 電子部品, 半導体
ETC5054 - ETC5057
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol
Parameter
IIXA Input Leakage Current
(–2.5V V +2.5V)
RIXA Input Resistance
(–2.5V V +2.5V)
ROXA Output Resistance (closed loop, unity gain)
RLXA
CLXA
Load Resistance
Load Capacitance
VOXA
AVXA
Output Dynamic Range (RL 10K)
Voltage Gain (VFXI+ to GSX)
FUXA Unity Gain Bandwidth
VOSXA Offset Voltage
VCMXA Common-mode Voltage
CMRRXA Common-mode Rejection Ratio
PSRRXA Power Supply Rejection Ratio
VFXI+ or VFXI-
VF XI+ or VFXI-
Min.
– 200
10
GS X
GS X
GS X
10
±2.8
5000
1
– 20
– 2.5
60
60
Typ.
1
2
Max.
200
3
50
20
2.5
Unit
nA
M
k
pF
V
V/V
MHz
mV
V
dB
dB
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol
RORF
RLRF
CLRF
VOSRO
Parameter
Output Resistance
Load Resistance (VFRO = ±2.5V)
Load Capacitance
Output DC Offset Voltage
VF RO
Min.
600
– 200
Typ.
1
Max.
3
500
200
Unit
pF
mV
POWER DISSIPATION (all devices)
Symbol
ICC0
IBB0
ICC1
IBB1
Power-down Current
Power-down Current
Active Current
Active Current
Parameter
Min.
Typ.
0.5
0.05
6.0
6.0
Max.
1.5
0.3
9.0
9.0
Unit
mA
mA
mA
mA
6/18

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ETC5054

SERIAL INTERFACE CODEC/FILTER

STMicroelectronics
STMicroelectronics
ETC5054D

SERIAL INTERFACE CODEC/FILTER

STMicroelectronics
STMicroelectronics
ETC5054N

SERIAL INTERFACE CODEC/FILTER

STMicroelectronics
STMicroelectronics


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