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PDF FAN1655 Data sheet ( Hoja de datos )
| Número de pieza | FAN1655 | |
| Descripción | 3A DDR Bus Termination Regulator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de FAN1655 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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FAN1655
3A DDR Bus Termination Regulator
www.fairchildsemi.com
Features
• Sinks and sources 2.1A continuous, 3A peak
• 0 to +125°C operating temperature range
• 5mA Buffered VREFOUT = VDDQ/2
• Load regulation: VTT = VREFOUT ± 40mV
• On-chip thermal limiting
• Low Cost SO-14, Power Enhanced eTSSOP or
8-pin 5x6mm MLP packages
• Low-Current Shutdown Mode
• Output Short Circuit Protection
Applications
• DDR Terminator VTT supply
Description
The FAN1655 is a low-cost bi-directional LDO specifically
designed for terminating DDR memory bus. It can both sink
and source up to 2.1A continuous, 3A peak, providing
enough current for most DDR applications. Load regulation
meets the JEDEC spec, VTT = VREFOUT ± 40mV.
The FAN1655 includes a buffered reference voltage capable
of supplying up to 5mA current. On-chip thermal limiting
provides protection against a combination of power overload
and ambient temperature that would create an excessive
junction temperature. A shutdown input puts the FAN1655
into a low power mode.
The FAN1655 regulator is available in a power-enhanced
eTSSOP™-16 package, and the standard SOIC-14
Block Diagram
VDDQ
VDD
VDD VDD SHDN
VREFOUT
VREFIN
200k
-
+
+
200k
FAN1655
VSSQ
-
VSS VSS VSS
VTTFORCE
VTTFORCE
VTTSENSE
REV. 1.1.3 2/20/03
1 page  
FAN1655
PRODUCT SPECIFICATION
Applications Information
Output Capacitor selection
The JEDEC specification for DDR termination requires that
VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay within
the 40mV window, the “load step” due to the load transient
current dropping across the output capacitor’s ESR should be
kept to around 25mV: where ESR < ∆-2---5-I is given in mΩ, and
∆I is the maximum load current.
For example, to handle a 3A maximum load transient, the
ESR should be no greater than 8mΩ. Furthermore, the output
capacitor must be able to hold the load in spec while the
regulator recovers (about 15µS). A minimum value of 470µF
is recommended.
These requirements can be achieved by a combination of
capacitors. FAN1655 requires a minimum of 5mΩ of ESR
in the output and is not stable with all-ceramic output
capacitors.
Power Dissipation and Derating
The maximum output current (sink or source) for a 1.25V
output is:
IOUT(MAX)
=
P----D----(--M----A----X----)
1.25
(1)
where PD(MAX) is the maximum power dissipation which is:
PD(MAX) = T----J---(-M-----Aθ----XJ--A-)---–-----T----A--
(2)
where TJ(MAX) is the maximum die temperature of the IC
and TA is the operating ambient temperature.
FAN1655 has an internal thermal limit at 150°C, which
defines TJ(MAX). For the SOIC-14 package, θJA is given at
88°C/W. Using equation 2, the maximum dissipation at
TA = 25°C is 1.4W, which is its rated maximum dissipation.
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the package
bottom. For maximum dissipation, this pad should be
soldered to the PCB copper, with as much copper area as
possible surrounding it to cool the package. Thermal vias
should be placed as close to the thermal pad as possible to
transfer heat to other layers of copper on the PCB. With large
areas of PCB copper for heat sinking, a θJA of under 40°C/W
can easily be achieved.
REV. 1.1.3 2/20/03
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet FAN1655.PDF ] | |
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